Principal Engineer, R&D Engineering (Static Timing Analysis)
SynopsysJob Title
Principal Engineer, R&D Engineering (Static Timing Analysis)
Role Summary
Lead architect and hands-on engineer responsible for defining and evolving major architectural components of a static timing analysis (STA) product used for sign-off of advanced silicon designs. Work with R&D leadership, distributed engineering teams, and customers to deliver scalable, high-performance timing analysis for multi-billion-cell SoCs.
The role focuses on technical strategy, algorithm development, system tradeoffs (accuracy, runtime, memory), and resolving tapeout-critical customer issues while mentoring engineering teams.
Experience Level
Senior-level. Requires 10+ years of relevant experience in EDA, system software, or similarly demanding technical domains.
Responsibilities
Accountable for architecture, design, and delivery of STA components and guiding technical direction.
- Own and evolve PrimeTime architectural components: timing engines, path search frameworks, constraint modeling, and distributed/parallel flows.
- Define long-term technical strategy for accuracy, capacity, runtime, and extensibility in STA.
- Drive architectural consistency across PrimeTime, compiler integration points, and sign-off ecosystems.
- Design and implement next-generation STA algorithms for multi-billion-cell designs and advanced timing effects.
- Resolve cross-cutting issues and make tradeoffs between accuracy, performance, memory footprint, and usability.
- Serve as technical authority for customer escalations, sign-off discrepancies, and tool correlations.
- Diagnose systemic SDC interpretation, timing convergence, path pessimism/optimism, and flow correlation problems.
- Mentor and influence engineers through reviews, design discussions, and leadership activities.
Requirements
Required technical skills and experience for immediate contribution.
- 10+ years of experience in EDA, system software, or equivalent technical domains.
- Deep hands-on experience with static timing analysis or closely related timing/circuit analysis technologies.
- Expert proficiency in C/C++ within large, performance-critical codebases.
- Proven track record of architecting complex systems and driving multi-year technical initiatives.
- Strong foundation in algorithms, data structures, and numerical analysis applied at scale.
- Ability to independently define, justify, and drive technical strategy and architectural decisions.
Preferred qualifications:
- Experience with PrimeTime or similar sign-off tools.
- Experience with distributed computing, parallel STA, and memory-scalable designs.
- Familiarity with advanced-node design challenges and tapeout-critical support.
Education Requirements
MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent demonstrated industry expertise (explicitly permitted by the posting).
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
