Principal Engineer, Physical Design
InnoPhase IoTJob Title
Principal Engineer, Physical Design
Role Summary
Lead full SOC physical implementation from RTL-to-GDS for low-power wireless SoCs, owning floorplan, place & route, CTS, signoff and physical verification. Work within a small cross-functional ASIC team to drive timing, power and area tradeoffs and enable production tapeouts.
Experience Level
Senior — requires extensive industry experience: typically 10+ years with a Master’s degree or 15+ years with a Bachelor’s degree (see Education Requirements for details).
Responsibilities
Primary hands-on responsibilities covering full-chip physical implementation, verification and signoff.
- Execute full physical implementation of block and chip level: synthesis, floorplanning, power delivery, place & route, CTS.
- Drive timing closure including ECO implementation and timing signoff (STA).
- Perform power integrity (IR), EM/noise/Signal EM analysis and remediation.
- Perform physical verification tasks: DRC, LVS, ERC, antenna checks and cleanup.
- Collaborate with SoC design and RTL teams to set timing/power/area targets and evaluate RTL/design tradeoffs.
- Analyze and optimize floorplan, clock tree structures and P&R quality.
- Support chip integration and signoff for production tapeouts.
Requirements
Must-have technical skills and domain experience. Education degree details are listed under Education Requirements below.
- Deep experience with power/ground grid design, partitioning, and physical verification flows.
- Proven netlist (or RTL)-to-GDS physical implementation experience, including full-chip floorplan, P&R, CTS and signoff on low-power SoCs.
- Strong knowledge of major EDA tools and design flows; strong Cadence experience/background.
- Experience with cutting-node processes (TSMC N22 or below) and related P&R/signoff considerations.
- Experience in chip integration and production signoff.
- Practical scripting/programming experience in Perl and TCL for automation and flow development.
- Preferred: expertise in low-power implementation methodology and advanced timing signoff techniques.
- Preferred: familiarity with DFT (BSCAN, MBIST, SCAN) and their physical-design impacts.
- Preferred: proven record completing multi-million gate design production tapeouts independently.
Education Requirements
Master's degree or above in Electrical Engineering or Computer Science with 10+ years of industry experience, or Bachelor's degree in Electrical Engineering or Computer Science with 15+ years of industry experience. (Degree + years requirement specified by employer.)
About the Company
Company: InnoPhase IoT
Headquarters: San Diego, California, United States
InnoPhase IoT is a dynamic company dedicated to harnessing cutting-edge technology within a collaborative environment. They emphasize innovation and creativity, providing opportunities for employees to work on diverse projects and celebrate their successes. With a focus on excellence, InnoPhase IoT is looking for talented individuals eager to contribute to a small yet powerful team.
