Principal Engineer - Physical Design
RenesasJob Title
Principal Engineer - Physical Design
Role Summary
Lead the physical implementation and delivery of large, high-performance SoCs on advanced process nodes, driving the flow from floorplanning through tape-out while meeting aggressive performance, power, area, and schedule targets.
Define chip-level methodologies, mentor senior engineers, and coordinate across architecture, RTL, verification, DFT, package, analog, and product teams to achieve implementation excellence.
Experience Level
Senior-level; typically 15–20+ years of ASIC/SoC physical design experience.
Responsibilities
Accountable for end-to-end physical design execution, implementation quality, and tape-out readiness.
- Lead full physical implementation from floorplanning to GDS signoff and tape-out readiness.
- Define implementation strategy, execution plans, schedules, and risk mitigation.
- Drive floorplanning, power planning, placement, clock tree synthesis, routing, and congestion management.
- Lead timing closure for complex multi-clock, high-frequency designs and perform signal integrity and IR/EM closure.
- Establish chip-level best practices and methodologies to meet frequency, power, and area goals.
- Collaborate with architecture, RTL, verification, DFT, package, analog, and product teams to optimize implementation and schedule.
- Partner with package and system teams to resolve package-level impacts and signal integrity issues.
- Lead physical design reviews, signoff activities, and mentor senior physical design engineers.
Requirements
Must-have technical skills and leadership experience required to deliver advanced-node, high-performance SoCs.
- 15+ years of ASIC/SoC physical design experience with a proven record of leading physical design teams and delivering large SoCs.
- Hands-on delivery experience on advanced nodes (3nm and/or 5nm) and deep understanding of advanced-node implementation challenges.
- Expertise in floorplanning, power planning, placement & optimization, CTS, routing, timing closure, signal integrity, IR/EM closure, and physical verification.
- Proven ability to manage complex execution schedules and drive tape-out readiness.
- Advanced low-power expertise: multi-voltage and multi-power-domain designs, DVFS, power gating and retention, clock gating, UPF/CPF low-power flows, leakage optimization, and power-aware physical closure.
- Experience integrating and closing timing on high-speed SerDes, mixed-signal/analog IP, and memory controller/high-speed interface blocks.
- Strong knowledge of industry-standard physical design and signoff flows and familiarity with package/system-level impacts on implementation.
Preferred: experience with NoC and large interconnects, advanced packaging and chiplet/multi-die architectures, AI/HPC/networking/datacenter products, and high-performance switch fabrics.
Education Requirements
Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related discipline.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
