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Principal Engineer, PHY/MAC Design

InnoPhase IoT
October 2, 2026
Full-time
On-site
San Jose, California, United States
$216,091 - $220,000 USD yearly
RTL Design Jobs, Level - Senior

Job Title

Principal Engineer, PHY/MAC Design

Role Summary

Lead PHY and MAC design for wireless ASIC and FPGA products, owning system-level modeling, DSP algorithm mapping, RTL micro-architecture, and verification to meet size, timing, and power targets. Work covers propagation/channel modeling, RF/antenna interactions, PHY and MAC protocols, and cross-team integration in a small-company engineering environment.

Salary range: $216,091–$220,000 per year. Up to 15% domestic travel.

Experience Level

Senior-level. Posting specifies a masters degree plus ten (10) years of relevant experience.

Responsibilities

Primary duties include system-level simulation, RTL development, verification support, and collaboration with physical-design teams.

  • Develop end-to-end simulation frameworks for wireless systems.
  • Design and map DSP algorithms across the signal chain from channel modeling and RF/antenna behavior to PHY and MAC protocols.
  • Define micro-architecture and implement SystemVerilog/RTL to meet size, timing, and power targets.
  • Analyze designs to identify bottlenecks and recommend micro-architecture optimizations.
  • Develop and refine design, verification, and analysis tools and flows.
  • Collaborate with Verification and Validation teams on test plans and coverage analysis.
  • Coordinate with Physical Design on floorplanning, constraints specification, and timing closure.
  • Support FPGA prototyping and ASIC development; travel up to 15% domestic.

Requirements

Must-have technical skills and hands-on experience.

  • Experience in ASIC development and/or FPGA prototyping.
  • RTL design experience using Verilog and SystemVerilog.
  • Strong understanding of digital signal processing theory and hardware mapping.
  • Experience with Wi‑Fi physical layer or other cellular/PHY implementations.
  • Familiarity with verification and analysis tools such as VCS, Verdi, Spyglass, or equivalents.
  • Experience in synthesis and timing closure for FPGA and ASIC flows.
  • Experience with front-end integration tasks: lint, CDC checks, synthesis, and developing timing ECOs.

Education Requirements

Masters degree in Electrical Engineering or a related field plus ten (10) years of relevant experience (as stated in the posting).


About the Company

Company: InnoPhase IoT

Headquarters: San Diego, California, United States

InnoPhase IoT is a dynamic company dedicated to harnessing cutting-edge technology within a collaborative environment. They emphasize innovation and creativity, providing opportunities for employees to work on diverse projects and celebrate their successes. With a focus on excellence, InnoPhase IoT is looking for talented individuals eager to contribute to a small yet powerful team.

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Date Posted: 2026-10-02