Principal Engineer – Multi-Physics Sign-off (Timing, PDN & Thermal)

Job Title

Principal Engineer – Multi-Physics Sign-off (Timing, PDN & Thermal)

Role Summary

Develop, enable, and support 3DIC and 2.5D physical design and signoff methodologies for advanced multi-die systems. Focus areas include timing, power (PDN/IR/EM), ESD, thermal, CFD/FEM, and coupled multiphysics analysis.

Work across physical design, package, power integrity, reliability, silicon, and EDA vendor teams to deliver robust, scalable, production-ready flows from floorplanning through tapeout.

Experience Level

Senior — Principal level. Guidance: minimum 5+ years of system-level experience.

Responsibilities

Accountable for developing, qualifying, and supporting multi-die implementation and signoff flows, automation, and cross-team enablement.

• Develop, maintain, and qualify CAD flows for 3DIC and 2.5D designs (chiplets, interposers, advanced packaging).
• Enable end-to-end implementation and signoff methodologies from floorplanning to tapeout, including cross-die timing and constraints.
• Support die-to-die connectivity, bump/TSV-aware flows, and cross-die constraint management.
• Develop and support STA, power analysis, IR drop, and EM signoff flows for multi-die systems.
• Define tool qualification, correlation, and signoff criteria; assist in tool upgrades, regressions, and migrations.
• Develop thermal and CFD/FEM methodologies; enable coupled electro-thermal and multiphysics flows.
• Build automation, scripts, checks, documentation, and training materials to improve flow robustness and usability.
• Provide CAD support during active design cycles and drive continuous improvement based on silicon takeaways.
• Collaborate with EDA vendors and internal teams to evaluate tools, features, and roadmap items.

Requirements

Must-have technical skills and experience required for immediate contribution.

Must-have:

• Minimum 5+ years of system-level experience working on physical implementation and signoff.
• Hands-on experience with 3DIC and/or 2.5D designs and chiplet-based or system-in-package architectures.
• Experience enabling timing (STA), power (IR/EM), and signoff flows for multi-die systems.
• Strong scripting and automation skills; proven flow ownership and debugging experience.
• Proven ability to collaborate across physical design, package, PI, reliability and vendor teams.

Nice-to-have:

• Experience with TSVs, micro‑bumps, interposers, and advanced packaging tradeoffs.
• Familiarity with industry EDA tools for 3DIC and thermal analysis (examples: Cadence Integrity 3D-IC, Synopsys 3DIC Compiler, Cadence Celsius, Ansys Icepak, Ansys RHSC-ET).
• Experience with CFD/FEM thermal modeling and coupled electro-thermal flows.

Education Requirements

Not specified.

About the Company

Company: Arm

Headquarters: Cambridge, United Kingdom

ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.