Principal Engineer (MTS), PDE Package Design

Job Title

Principal Engineer (MTS), PDE Package Design

Role Summary

Lead package architecture and execution for PDE package designs from feasibility through tape-out, qualification, and production readiness. Drive silicon–package–board co-design and lead cross-functional technical decisions across product, silicon, technology, assembly, quality, suppliers, and OSAT partners.

Experience Level

Senior - minimum 10 years of relevant experience in package architecture and silicon–package co-design.

Responsibilities

Responsible for technical leadership, design delivery, and process improvement in package design.

• Own package architecture and execution through feasibility, tape-out, qualification, and production handoff.
• Serve as technical authority on complex package issues; lead cross-functional reviews, trade-off decisions, and risk closure.
• Integrate floorplan, interface, interconnect, power, signal, thermal, and mechanical requirements for silicon–package–board co-design.
• Advance design rules, methodologies, automation workflows, and technology roadmaps for future products.
• Mentor engineers and influence roadmaps, standards, and investment decisions across the organization.
• Apply AI-enabled tools responsibly to research, analysis, and operational tasks; identify and share efficiency improvements.

Requirements

Must-have technical skills and demonstrated outcomes.

• Minimum 10 years relevant experience in package architecture and silicon–package co-design.
• Deep expertise in feasibility, stack-up, I/O and interconnect planning, substrate layout, routing, power delivery, signal return paths, and design verification.
• Hands-on experience with multiple package technologies and knowledge of manufacturability, assembly processes, substrates, materials, reliability, and failure mechanisms.
• Proven ownership of complex package designs from feasibility and trade-off studies through NPI tape-out, qualification, and manufacturing handoff.
• Advanced proficiency with Cadence Allegro Package Designer / SiP Layout or equivalent package-design tools and design-rule/review workflows.
• Strong technical leadership, mentoring, and stakeholder communication skills; ability to influence without direct authority and demonstrate organization-wide impact.
• Experience integrating AI-assisted tools into workflows while exercising sound judgment and complying with organizational standards.

Education Requirements

Master's degree in Electrical Engineering, Mechanical Engineering, Materials Engineering, or a related discipline; PhD candidates welcome.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.