Principal Engineer/Manager - Design Verification
RenesasJob Title
Principal Engineer/Manager - Design Verification
Role Summary
Lead a verification organization responsible for functional verification of complex digital IPs, subsystems, and SoC solutions. Drive verification strategy, execution, and sign-off while coordinating with architecture, design, firmware, emulation, validation, and program teams to achieve first‑silicon success.
Experience Level
Senior-level. Requires extensive design verification experience; the posting specifies 15+ years in verification with at least 3–5 years in technical leadership or people management.
Responsibilities
Primary responsibilities include ownership of verification strategy and team leadership across complex SoC projects.
- Own verification strategy, planning, execution, and sign-off for complex SoCs and subsystems.
- Define verification plans aligned with architecture and product requirements.
- Drive adoption of verification methodologies (UVM, SystemVerilog, assertions, coverage-driven methods, formal, emulation).
- Establish verification metrics, coverage goals, and quality benchmarks.
- Review verification architectures, testbench frameworks, reusable IP, and coverage models.
- Lead root-cause analysis and resolution of critical functional issues.
- Build, mentor, and retain a high-performing verification team; handle performance reviews and career development.
- Track project schedules, risks, resource plans, and provide status to senior leadership to ensure tape-out readiness.
- Drive automation, improve regression/debug workflows, and promote verification reuse and productivity improvements.
Requirements
Must-have technical skills, leadership experience, and delivery track record.
- 15+ years of experience in design verification with proven delivery from specification through silicon validation.
- 3–5+ years of technical leadership or people management experience.
- Expertise in SystemVerilog and UVM methodology; functional coverage and assertions.
- Hands-on experience with simulation, emulation, and formal verification techniques.
- Experience verifying complex digital designs, IPs, subsystems, or SoCs and strong microarchitecture debugging skills.
- Proficiency with scripting languages such as Python, Perl, Tcl, or Shell for automation and flows.
- Proven ability to define verification metrics, close coverage, and meet project milestones.
- Strong cross-functional collaboration and stakeholder management skills.
- Preferred (nice-to-have): experience with automotive SoCs/MCUs, ISO26262 familiarity, mixed-signal verification, FPGA prototyping/emulation, and managing distributed teams.
Education Requirements
Bachelor's or Master's degree in Electronics Engineering or Electrical Engineering.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
