Principal Engineer, High-Speed RTL Design

Job Title

Principal Engineer, High-Speed RTL Design

Role Summary

Design and implement timing-critical RTL blocks for high-speed SoC and memory interface subsystems. Work with verification, synthesis, and integration teams to achieve timing closure and reliable operation in advanced nanometer processes.

This role is part of an RTL design team based in Bengaluru focused on high-speed, low-latency control logic, power- and clock-aware implementations, and robust integration into larger systems.

Experience Level

Senior-level (Principal). Years of experience not specified.

Responsibilities

Deliver robust, timing-aware RTL and support integration, verification, and timing closure activities.

• Design and implement timing‑critical RTL blocks: FSMs, power‑up/shutdown/mode‑transition logic, register banks, configuration logic, telemetry/monitoring datapaths.
• Write nanometer-process-aware RTL tolerant to tight setup/hold margins, clock skew, multi‑cycle/false paths, and PVT variation.
• Implement and review clock‑domain crossings, reset/initialization logic, and power/mode-dependent behavior.
• Integrate RTL into top-level designs and resolve port, clock/reset, and mode interaction issues.
• Debug RTL and integration problems using simulation waveforms and tool feedback.
• Work with verification engineers to clarify intent, fix RTL bugs, and address timing issues discovered during synthesis/place‑and‑route.
• Participate in design reviews and maintain concise documentation of block functionality and assumptions.

Requirements

Must-have technical skills and practical experience for successful performance in this role.

• Must-have: Strong proficiency in SystemVerilog/Verilog RTL and RTL design for timing‑critical control logic.
• Experience with FSM design and implementation, reset synchronization, and clock‑domain crossing concepts.
• Solid understanding of setup/hold timing fundamentals, critical‑path sensitivity, and multi‑mode behavior.
• Familiarity with RTL lint, CDC checks, synthesis flows, and basic static timing analysis (STA) reports.
• DFT‑friendly RTL practices, UPF and LEC awareness, and ability to debug issues during RTL sign‑off or late integration.
• Nice-to-have: Exposure to PMICs, mixed‑signal SoCs or companion ICs; basic scripting (Python/Tcl); experience with RTL–DV–PD handoffs and AI-enabled engineering tools.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.