Principal Engineer - HIG HBM - Architecture

Job Title

Principal Engineer - HIG HBM - Architecture

Role Summary

Define and drive the architecture of high-speed analog and mixed-signal IO subsystems for next-generation High Bandwidth Memory (HBM) products. Work across design, verification, packaging, product engineering, modeling, and system architecture teams to translate architectural decisions into silicon.

As a technical leader you will set PHY IO architecture and timing methodology, develop analog calibration and silicon-learning frameworks, influence product roadmaps, and mentor engineering teams.

Experience Level

Senior - 7+ years of semiconductor design, architecture, or technology development experience.

Responsibilities

Primary responsibilities include defining architecture, driving cross-functional execution, and establishing methodologies for high-speed IO and HBM interfaces.

• Define and drive next-generation HBM PHY and IO architecture balancing performance, power, area, reliability, and manufacturability.
• Architect high-performance transmit and receive paths, including clocking, signaling, equalization, timing alignment, and interface optimization.
• Define and optimize analog calibration architectures: impedance, reference voltage, timing calibration, and adaptive/background tuning.
• Develop and maintain IO timing budgets, design targets, and margin methodologies across process, voltage, temperature, and package variations.
• Collaborate with modeling, verification, packaging, and product engineering teams to ensure architecture translates to silicon successfully.
• Provide technical leadership, mentorship, and documentation of architectural principles and best practices.

Requirements

Core technical requirements and preferred skills.

• 7+ years of experience in semiconductor design, architecture, or technology development.
• Demonstrated expertise in analog and mixed-signal IO design and architecture.
• Deep knowledge of high-speed transmitter, receiver, clocking, and timing architectures.
• Experience with analog calibration schemes and adaptive/background calibration techniques.
• Experience developing IO timing budgets and margin methodologies across PVT and packaging.
• Strong technical communication and documentation skills; experience mentoring engineers.

Preferred:

• Experience with HBM, DDR, UCIe, PCIe, or other high-speed memory and interconnect technologies.
• Advanced packaging experience (2.5D, 3D integration, TSV-based systems) and silicon bring-up/post-silicon debug.
• Background in clock generation, PLLs, phase alignment, or timing recovery circuits.
• Experience with simulation-to-silicon correlation, modeling, and silicon characterization.
• Use of AI-enabled analytics or automation to improve design quality or silicon analysis.
• Experience developing design methodologies, architecture standards, and training materials.

Education Requirements

MS or PhD in Electrical Engineering or a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.