Principal Engineer, Front-end and Back-end SoC Engineering

Job Title

Principal Engineer, Front-end and Back-end SoC Engineering

Role Summary

Lead technical strategy and execution for end-to-end SoC and ASIC projects from architecture through GDS tapeout. Serve as the technical lead for cross-functional, geographically distributed teams delivering complex, multi‑billion transistor designs at advanced process nodes.

Work with customers, internal product and sales teams, and subcontractors to define implementation approaches that meet performance, power, area, quality, schedule, and cost targets.

Experience Level

Senior — requires 15+ years of semiconductor industry experience leading complex SoC/ASIC projects through successful tapeout.

Responsibilities

Primary technical and delivery responsibilities for SoC design engagements.

• Provide technical leadership for end-to-end SoC/ASIC development including strategy, methodology, and execution to tapeout.
• Define and drive front-end activities: SoC architecture, IP subsystem integration and hardening, RTL development, functional verification planning, and DFT with scan/ATPG.
• Own back-end physical implementation: floorplanning, hierarchical partitioning, place & route, CTS, PPA optimization, and timing closure using Synopsys tools.
• Develop and manage constraints for functional and DFT modes; own STA, IR-drop, EM analysis, DRC/LVS signoff, formal, and ECO strategies.
• Manage schedules, risks, dependencies, and resources across distributed engineering teams and external partners.
• Interface with customers, sales, IP and EDA teams to align technical decisions and tapeout readiness.
• Conduct technical reviews and make design trade-offs to balance performance, power, area, quality, schedule, and cost.
• Support technical presales by gathering requirements and preparing effort estimates.

Requirements

Must-have technical skills and domain experience. Education details are listed under Education Requirements below.

• 15+ years leading complex SoC or ASIC projects through tapeout (leadership and delivery focus).
• Extensive hands-on experience in both front-end and back-end implementation.
• RTL design and verification knowledge (Verilog/SystemVerilog) and DFT experience.
• Physical design and timing signoff expertise, including multi-corner multi-mode timing closure, IR-drop and EM mitigation.
• Direct experience integrating and hardening high-speed subsystems (PCIe, DDR, UCIe, Ethernet).
• Proficiency with Synopsys EDA tools such as Fusion Compiler, PrimeTime, PrimePower, VCS, Formality, Redhawk SC, TestMax, VC Spyglass.
• Experience coordinating geographically distributed teams and external subcontractors; strong communication and customer-facing skills.

Nice-to-have:

• Experience with Platform Architect, DSO.ai, Fusion.ai, RTLA, TCM, Git/GitHub/Copilot.
• Background with multi-billion transistor SoCs, chiplet architectures, advanced packaging, AI/ML, automotive, HPC, networking, datacenter products, or ISO 26262.

Education Requirements

Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.