Principal Engineer / Director, Physical Design (Custom Silicon Group)
QualcommJob Title
Principal Engineer / Director, Physical Design (Custom Silicon Group)
Role Summary
Lead physical design and signoff for next-generation SoCs from architecture to tapeout. Manage and grow a multi-site engineering team and coordinate cross-functional activities (RTL, verification, CAD, integration, firmware/software) to achieve timing, power, and area signoff.
This is a customer-facing technical leadership role responsible for physical implementation strategy, design convergence, and production readiness on advanced process nodes.
Experience Level
Senior (Principal / Director level). The posting indicates senior leadership with multi-site management and long-tenure engineering experience; see Education Requirements for the specific experience ranges cited.
Responsibilities
Accountabilities include end-to-end physical design delivery, technical leadership, and customer engagement.
- Lead and manage multi-function, multi-site physical design teams.
- Own placement & route implementation: floorplanning, placement, CTS, routing and post-route activities through tapeout.
- Drive signoff across STA, power analysis, formal/functional verification, low-power verification and physical verification.
- Resolve constraints, timing, and physical-design issues across RTL, verification, CAD, and integration groups.
- Address deep sub-micron challenges including leakage, signal integrity, and DFM.
- Provide technical leadership during design reviews and in executive-level customer engagements.
- Support pre-sales/business-development evaluation of technical feasibility and design trade-offs.
- Coordinate cross-team resolution of customer-reported issues through silicon bring-up and validation.
Requirements
Must-have technical skills and experience (degree details are summarized under Education Requirements).
- Extensive hands-on experience in physical design, placement/CTS, and PnR implementation on advanced technology nodes.
- Proven signoff expertise in STA and power analysis and ability to drive signoff closures.
- Experience leading teams and delivering across multiple sites and functions.
- Practical knowledge of timing closure, low-power and high-performance optimizations, and post-route validation.
- Strong collaboration and communication skills for customer engagements and cross-functional coordination.
- Preferred: experience with latest nodes (2nm–5nm), LEC/CLP/PDN signoff domains, and pre-sales technical support.
Education Requirements
The posting lists Bachelor's, Master's and PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field (or equivalent practical experience). It specifies multiple experience thresholds: bachelor-level with ~8+ years, master's with ~7+ years, PhD with ~6+ years in one section; elsewhere it cites principal-level expectations of ~17–25 years and preferred 18+ years of physical-design/timing-signoff experience on advanced nodes. Equivalent practical experience is implicitly acceptable.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
