Principal Engineer, Digital IC Design

Job Title

Principal Engineer, Digital IC Design

Role Summary

Lead digital IC design and SoC integration efforts within the Custom Compute, Storage and Automotive Business Unit. Drive portions of SoC designs from micro-architecture through tape-out, coordinate cross-disciplinary teams, and own block-level and chip-level implementation and debug.

Experience Level

Senior — principal-level role. Typical experience: 10–15 years (with a Bachelor's) or 5–10 years (with a Master's/PhD) in digital IC/SoC design and integration.

Responsibilities

Technical and leadership responsibilities focused on delivering high-quality SoCs to tape-out.

• Take ownership of a portion of an SoC and drive it from specification through tape-out.
• Design RTL (SystemVerilog) for processor/IP blocks and deliver micro-architectural specifications.
• Integrate internal and external IP blocks, including interconnect and clock/reset networks.
• Work with floorplanning, perform static checks, CDC analysis, and drive timing closure.
• Support subsystem and chip-level verification and post-silicon debug activities.
• Collaborate with architecture, physical design, verification, DFT, and packaging teams.
• Develop and use automation and internal EDA tools; incorporate AI/automation where appropriate.
• Mentor and provide technical leadership to junior engineers.

Requirements

Core technical skills and practical experience required for the role.

• Proven experience in taping out complex SoCs and post-silicon debug.
• Strong RTL design skills in SystemVerilog and understanding of front-end implications on implementation and verification.
• Hands-on SoC integration and debug experience, including clock/reset design, CDC, and timing constraints.
• Familiarity with ARM protocols (APB, AHB, AXI, CHI) and SoC interconnect/NOC architectures.
• Experience with scripting (Python or Tcl) to support automation and flows.
• Excellent communication, analytical, and problem-solving skills; demonstrated ability to lead technical teams.
• Experience with industry and internal EDA tools for functional and gate-level simulation and code/CDC checks.

Education Requirements

Bachelor’s degree in Electrical Engineering, Electronics, Computer Engineering, or a related technical field (typical 10–15 years of experience). Alternatively, a Master’s degree and/or PhD in these fields with approximately 5–10 years of relevant experience. Related fields and advanced degrees are explicitly referenced in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.