Principal Engineer, Design Verification Engineering

Job Title

Principal Engineer, Design Verification Engineering

Role Summary

Lead verification for complex digital SoC and subsystem designs, defining verification architecture, flows, and methodology and driving verification from planning through signoff. Work cross-functionally with architecture, design, emulation, FPGA, firmware and software teams to ensure pre-silicon readiness and system-level correctness.

Experience Level

Senior — typically requires 12+ years of experience in digital pre-silicon verification and leadership across IP, subsystem, or SoC-level DV.

Responsibilities

Deliver end-to-end verification for complex SoCs and subsystems, mentor and lead verification engineers, and introduce scalable methodologies and flows.

• Lead verification planning, execution, and closure from test-plan definition to signoff for SoC/subsystem projects.
• Architect and implement scalable UVM-based testbenches and DV flows; ensure functional and code coverage closure.
• Verify microprocessor-based designs, AI/ML accelerators, NoC/interconnects, and high-speed peripherals.
• Coordinate with emulation, FPGA, software, and system teams to cover system-level and post-silicon scenarios early.
• Apply formal verification techniques and integrate them into verification strategy where appropriate.
• Drive performance verification and system-level analysis across representative use cases.
• Define and review test plans; track coverage metrics and optimize verification closure.
• Mentor, provide technical leadership, and drive verification methodology adoption across teams.

Requirements

Must-have technical skills, tools, and leadership qualities expected for immediate contribution and team leadership.

• Must-have: Hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, constrained-random verification, assertions, and coverage-driven verification.
• Must-have: Proven record of verification closure using functional and code coverage metrics at block, subsystem, and SoC levels.
• Must-have: Experience with NoC, bus, and interconnect verification and coverage analysis.
• Must-have: Familiarity with formal verification, flow definition, and property checking.
• Must-have: Protocol verification experience (examples: AXI/AHB, DMA, Ethernet, I2C, SPI, UART, SVI3) and gate-level simulation familiarity.
• Must-have: Proficiency in C/C++, SystemC and scripting (Python, TCL, Shell) for verification infrastructure and test generation.
• Must-have: Strong leadership, communication, and cross-functional collaboration skills.
• Nice-to-have: Power-aware verification experience (UPF), exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY), and experience with AI/ML accelerators and processor-based systems (ARM, RISC-V, Tensilica).
• Willingness to travel up to 10%.

Education Requirements

B.Tech or M.Tech degree. The posting indicates 12+ years of relevant digital pre-silicon verification experience.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.