Principal Engineer, Design Verification
Lead SoC-level design verification efforts in the Custom Compute, Storage and Automotive Business Unit. Responsible for developing and maintaining UVM testbench components, verification collateral, and methodologies for complex SoC architectures used in compute, storage, networking and automotive applications.
Senior — typically 7+ years (with a Master's/PhD) or 10+ years with a Bachelor's; significant SoC-level verification experience expected.
Primary responsibilities include planning, building, and executing verification environments and tests for SoC designs.
Must-have technical skills and demonstrated experience.
Bachelor's degree in Computer Science, Electrical Engineering or related field with 10+ years of related professional experience; or a Master’s degree or PhD in Computer Science, Electrical Engineering or related fields with 7+ years of related experience.
Company: Marvell Technology
Headquarters: Santa Clara, California, United States
Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.
