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Principal Engineer - Design Verification

Renesas
July 21, 2026
Full-time
On-site
Hyderabad, Telangana, India
Verification Jobs, Level - Senior

Job Title

Principal Engineer - Design Verification

Role Summary

Lead verification engineering for SoC and MCU projects, defining verification plans, driving execution, and delivering quality sign-offs. Work closely with system architects and cross-functional R&D teams (RTL, DFT, IP, PD, emulation, validation) to ensure designs meet specifications.

The role directs verification methodology adoption, collaborates with EDA vendors, and reports technical progress and risks to stakeholders.

Experience Level

Senior — typically requires 14+ years of experience in SoC verification and related domains.

Responsibilities

Accountable for technical leadership and delivery of SoC verification activities.

  • Define and own detailed SoC verification plans, milestones, progress reporting, and risk mitigations.
  • Drive adoption of verification methodologies and best practices across global teams.
  • Collaborate with system architects to translate high-level specs into verification objectives and tests.
  • Coordinate with RTL, DFT, digital IP, physical design, emulation, and validation teams to meet project targets.
  • Work with EDA vendors to evaluate and deploy verification tools and flows.
  • Perform coverage closure, requirements traceability, and gate-level simulation activities.
  • Provide technical presentations and executive-level updates on verification status and quality.

Requirements

Must-have technical skills and experience for successful performance in this role.

  • Extensive experience with microcontroller and microprocessor architectures and interconnects, including work on complex multi-core SoCs with many peripherals.
  • Strong experience with protocols such as AHB/AXI and memory subsystems (ROM, RAM, Flash, MRAM) and memory controllers.
  • Advanced proficiency in Verilog/SystemVerilog, and strong C/C++ skills; Shell scripting for flow automation.
  • Proven testbench design and development experience using UVM for IP/subsystem and SoC verification.
  • Deep knowledge of metric-driven verification: functional and code coverage, directed and constrained-random methodologies.
  • Familiarity with formal verification methodologies and assertions; experience debugging designs pre- and post-silicon.
  • Strong written and verbal communication skills and ability to lead cross-functional technical efforts.

Nice-to-have:

  • Scripting experience in Perl, TCL, or Python.
  • Experience delivering reusable production-quality VIPs across multiple SoCs.

Education Requirements

Bachelor's or master’s degree in electronics engineering.


About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.

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Date Posted: 2026-07-21