Principal Engineer - Design Verification

Job Title

Principal Engineer - Design Verification

Role Summary

Lead verification strategy and execution for UA Link Switch products within the Memory Interface Division (MID). Responsible for verification architecture, testbench development, coverage planning, and verification closure for large-scale digital subsystems and SoCs.

Primary mission: ensure first-silicon success for high-performance, high-bandwidth interconnect and switching solutions by driving verification planning, execution, and cross-functional coordination.

Experience Level

Senior — 18+ years of ASIC/SoC verification experience, proven leadership delivering complex verification programs from architecture through tape-out.

Responsibilities

Accountable for verification strategy, execution, and team leadership across complex SoC/subsystem projects.

• Define and own verification strategy, methodology, and execution plan for UA Link Switch products.
• Lead verification architecture, scalable UVM/SystemVerilog testbench development, and coverage planning.
• Develop verification plans covering functionality, performance, reliability, error handling, and corner-case scenarios.
• Drive simulation, regression infrastructure, and verification-closure activities.
• Lead debug and root-cause analysis of design and verification issues; support silicon bring-up readiness.
• Define and track verification metrics (functional coverage, code coverage, assertions, regression quality).
• Collaborate with architecture, design, firmware, system validation, and silicon bring-up teams to ensure comprehensive coverage.
• Lead verification reviews, sign-off activities, and silicon readiness assessments.
• Mentor verification engineers and establish verification best practices across the organization.

Requirements

Must-have technical skills, experience, and responsibilities required for the role.

• 18+ years of ASIC/SoC verification experience with proven leadership of complex verification programs.
• Hands-on expertise in SystemVerilog and UVM; strong use of Assertion-Based Verification (SVA).
• Deep experience with functional and code coverage methodologies, simulation and regression infrastructure, and verification-closure techniques.
• Experience verifying large-scale digital systems: high-speed digital designs, SoCs/subsystem integration, switching fabrics, memory controllers/subsystems.
• Strong understanding of RTL design concepts and hardware architecture.
• Proven ability to drive cross-functional technical teams and influence architecture and design decisions.
• Experience mentoring engineers and leading verification teams towards tape-out readiness.

Nice-to-have / preferred:

• Experience with high-speed SerDes-based systems, switching fabrics, packet-based architectures, or memory interface technologies.
• Familiarity with AI/HPC interconnects, PCIe, CXL, Ethernet, UALink, UCIe, or similar protocols.
• Experience with formal verification, emulation, FPGA prototyping, performance/system-level validation, and post-silicon debug.
• Hands-on experience with mixed hardware/firmware verification environments and leading geographically distributed teams.

Education Requirements

Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field (e.g., Computer Science, Electronics). (Degrees explicitly listed in the source.)

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.