Principal Engineer, Design Verification

Job Title

Principal Engineer, Design Verification

Role Summary

Verify complex digital SoC and IP designs across AI/ML, networking, compute, memory expander and accelerated compute product lines. Build verification architectures, reference models, bus-functional monitors/drivers, and testbenches using SystemVerilog and UVM.

Lead verification efforts for multicore SoCs, debug silicon/design failures, develop tooling to improve verification efficiency, and mentor a geographically distributed verification team.

Experience Level

Senior. The posting requires at least 5 years of relevant design verification experience in addition to the technical skills listed below.

Responsibilities

Primary responsibilities focus on architecture and execution of functional verification for complex SoCs and IP.

• Design verification planning and architecture of UVM-based test environments and reference models.
• Create and execute detailed verification test plans using constrained-random techniques and coverage-driven methods.
• Develop monitors, drivers, and verification IP for buses and protocols; tune environments to meet coverage goals.
• Debug functional failures, work with designers to triage and resolve issues, and drive regressions.
• Develop and maintain verification automation and productivity tools for multicore SoC flows.
• Mentor and technically lead verification engineers across multiple locations.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Minimum five (5) years of hands-on experience in complex/random verification environments using SystemVerilog and UVM.
• Proven ability to write and execute detailed verification test plans and achieve coverage goals.
• Experience with scripting (Python or Perl), EDA verification tools, bug tracking and regression systems.
• Object-oriented design and implementation experience; C/C++ for modeling and processor-resident code.
• Verification experience with subsystems such as ARM/processor, memory, networking, NoC, and cache systems.
• Familiarity with high-speed protocols: PCIe, Ethernet, DDR, HBM.
• Experience with version control systems (CVS, Perforce, Git) and ASIC development processes, tools, and methodologies.
• Knowledge of low-speed interfaces (SPI, UART, I2C, I3C, JTAG) and interconnect/bus protocols (AXI, ACE, AHB, APB, NIC-400).
• Ability to analyze complex SoC architecture, memory and peripheral interfaces and drive root-cause analysis.
• Must be eligible for access to export-controlled technology; candidates may be subject to export license reviews.

Education Requirements

Master's degree or foreign equivalent in Computer Science, Electrical Engineering, or a related technical field, plus five (5) years of relevant experience as stated in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.