Principal Engineer, Design Technology Co-optimization

Job Title

Principal Engineer, Design Technology Co-optimization

Role Summary

Lead the optimization of standard cell libraries and drive design-technology co-optimization (DTCO) for Intel Foundry advanced process nodes. Work within the Advanced Design & Foundational IP (ADFIP) organization to improve power, performance, and area (PPA) across silicon and packaging, and coordinate with internal technology teams, EDA partners, and foundry customers.

Experience Level

Senior — 10+ years of industry experience.

Responsibilities

Primary responsibilities focus on optimization of library IP and customer-facing technical leadership.

• Drive optimization and tuning of standard cell libraries for advanced process nodes.
• Engage directly with foundry customers to identify technology and library gaps and requirements.
• Collaborate with process and physical design teams to deliver layout and cell optimizations that improve PPA and manufacturability.
• Work with EDA partners to optimize cell content and characterization flows to improve product-level technology entitlement.
• Define and prioritize cell design changes and verification flows to meet product signoff goals.
• Provide technical leadership across cross-functional teams and drive delivery of library projects.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Strong understanding of advanced semiconductor technology and foundation IP design.
• Experience in standard cell library design and familiarity with MOSFET electrical behavior, local layout effects, and variability at advanced nodes.
• Experience with library cell characterization methods, SPICE circuit simulation, and related tools.
• Practical familiarity with the semiconductor foundry ecosystem (foundry, EDA/IP, or foundry customer perspective).
• Excellent oral and written communication skills and a collaborative, team-oriented mindset.
• Demonstrated technical leadership and track record of delivering complex IP or library projects.

Nice-to-have:

• Experience with product designs, signoff methodology, and tradeoffs across power, performance, and area.
• Familiarity with pre- and post-silicon foundry benchmarking and foundation IP silicon validation.
• Experience identifying, designing, and verifying cells targeted to improve product-level PPA and with EDA tool integration for cell optimization.

Education Requirements

Ph.D. or master’s degree in Electrical Engineering or Computer Science. The posting also specifies 10+ years of industry experience. (No alternative "equivalent experience" language was provided.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.