Principal Engineer - Design (FPGA)

Job Title

Principal Engineer - Design (FPGA)

Role Summary

Senior FPGA design engineer to lead FPGA-based platform development for PHY (Physical Layer) and system-level solutions supporting next-generation USB and Ethernet products. Work closely with digital, analog, firmware, ASIC, verification, and validation engineers to develop, integrate, and validate FPGA designs and lab bring-up on mixed-signal IP and SoC platforms.

Experience Level

Senior level — requires 10+ years of FPGA and/or digital design experience as specified in the qualifications.

Responsibilities

The role focuses on FPGA RTL development, simulation, synthesis, board-level integration, and lab validation for PHY and SoC projects.

• Develop synthesizable RTL (Verilog/SystemVerilog) for FPGA-based prototypes and platforms.
• Create and run self-checking testbenches; perform functional simulation and debug.
• Perform FPGA synthesis, implementation, timing analysis, and place-and-route using vendor tools (e.g., AMD/Xilinx Vivado).
• Define and analyze timing constraints; design and verify multi-clock-domain systems.
• Integrate FPGA designs with mixed-signal IP and SoC components; support board-level bring-up and system integration.
• Use laboratory debug equipment (oscilloscopes, logic analyzers, protocol analyzers, embedded logic-debug) for hardware validation and troubleshooting.
• Produce clear design documentation: requirements, FPGA architecture, block diagrams, and interface control documents.

Requirements

Must-have technical skills and experience required for the role; a small set of preferred items is noted separately.

• 10+ years of FPGA and/or digital design experience with hands-on RTL coding, simulation, synthesis, and hardware implementation.
• Strong proficiency in Verilog and/or SystemVerilog for synthesizable RTL.
• Solid understanding of digital design fundamentals: state machines, datapaths, pipelines, clocking, resets, FIFOs, memories, and interface logic.
• Experience developing self-checking testbenches and using simulation tools such as QuestaSim/ModelSim or equivalent.
• Hands-on experience with FPGA synthesis, implementation, timing analysis, and place-and-route (e.g., Vivado).
• Experience defining timing constraints and designing for multiple clock domains; optimizing for performance and resource utilization.
• Experience with FPGA system integration and board-level bring-up, including loading FPGA images and debugging on physical circuit cards.
• Proficiency with scripting/automation: TCL and one or more of Python or Perl; familiarity with Linux shell. Familiarity with C++ or Rust for automation is a plus.
• Experience with revision-control systems such as Perforce, Git, DesignSync, including tagging/branching and release methodologies.
• Strong verbal and written communication skills; ability to participate in technical discussions and design reviews and produce technical documentation.
• Travel expectation: approximately 0%–25%.

Nice-to-have

• Experience with USB and Ethernet PHY architectures and protocols.

Education Requirements

Not specified.

About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.