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Principal Engineer - Design (FPGA)

Microchip
August 22, 2026
Full-time
On-site
Chandler, Arizona, United States
RTL Design Jobs, Level - Senior

Job Title

Principal Engineer - Design (FPGA)

Role Summary

Microchip's NCS team seeks a Principal FPGA Design Engineer to lead FPGA-based platform development for PHY and SoC verification, integration, and system-level validation targeting USB and Ethernet products. This position is based in the Chandler Design Center and works closely with digital, analog, firmware, software, and validation teams.

Primary responsibilities include architecting FPGA test platforms, RTL implementation and verification, board bring-up, and supporting lab debug and system integration.

Experience Level

Senior level. The posting requests 10+ years of experience in FPGA and/or digital design.

Responsibilities

Deliver and validate FPGA-based solutions that exercise mixed-signal IP and system-level functionality.

  • Design and implement synthesizable RTL and testbench infrastructure for FPGA platforms.
  • Integrate FPGA platforms with analog, ASIC, firmware, and software components for system-level validation.
  • Perform simulation, synthesis, timing closure, and place-and-route flows; define and analyze timing constraints across multiple clock domains.
  • Lead FPGA board-level bring-up: load images, exercise interfaces, and debug hardware on circuit cards.
  • Develop self-checking testbenches and perform functional simulation and debug using QuestaSim/ModelSim or equivalent tools.
  • Use lab equipment (oscilloscopes, logic analyzers, protocol analyzers, embedded logic-debug) for hardware validation and debugging.
  • Document designs: requirements, FPGA architecture, block diagrams, and interface control documents.
  • Collaborate in design reviews and provide project updates to cross-functional teams.

Requirements

Must-have skills, tools, and experience for immediate contribution.

  • 10+ years of FPGA and/or digital design experience with hands-on RTL coding, simulation, synthesis, and hardware implementation.
  • Proficiency in Verilog and/or SystemVerilog for synthesizable RTL.
  • Experience creating self-checking testbenches and using QuestaSim/ModelSim or equivalent for functional verification.
  • Hands-on FPGA synthesis, implementation, timing analysis, and place-and-route using vendor tools (e.g., AMD/Xilinx Vivado).
  • Strong understanding of digital design fundamentals: state machines, datapaths, pipelines, clocking, resets, FIFOs, memories, and interface logic.
  • Experience defining timing constraints and designing across multiple clock domains; ability to optimize for performance and resource utilization.
  • Board-level bring-up and FPGA system integration experience, including loading FPGA images and exercising hardware interfaces.
  • Proficient with laboratory debug tools (oscilloscopes, logic analyzers, protocol analyzers) and FPGA embedded debug features.
  • Scripting and automation skills (TCL, Python, Perl); familiarity with Linux shell. Experience with C++ or Rust for automation is beneficial.
  • Knowledge of revision-control systems (Perforce, Git, DesignSync or equivalent) including tagging/branching and configuration management.
  • Strong verbal and written communication skills and experience participating in technical discussions and design reviews.

Nice-to-have

  • Experience with USB and Ethernet PHY architectures and protocols.

Education Requirements

Not specified.


About the Company

Company: Microchip

Headquarters: Chandler, Arizona, USA

Microchip is a leading semiconductor company focused on developing innovative solutions to enhance the human experience. With a commitment to empowering innovation, Microchip prioritizes the value of its employees by fostering a culture that supports their growth and contributions.

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Date Posted: 2026-08-21