Principal Engineer - Design For Test (DFT)

Job Title

Principal Engineer - Design For Test (DFT)

Role Summary

Senior DFT engineer responsible for defining and implementing design-for-test (DFT) solutions for complex custom ASIC/SoC and multi-die designs. Member of the Custom Silicon Engineering team working on high-performance compute, AI, and carrier platforms.

Primary focus: DFT architecture, insertion and verification, pattern generation, and post-silicon bring-up and debug across chiplet and 2.5D/3D designs.

Experience Level

Senior. Posting requests a minimum of 10 years of work experience overall and at least 8 years of direct DFT experience in custom ASIC design.

Responsibilities

Deliver and support DFT implementation and verification across IP and SoC projects.

• Define and implement DFT architecture and DFX features for complex ASIC/chiplet designs.
• Insert DFT structures and run Tessent-based flows (including Tessent SSN) and related toolchains.
• Develop and execute verification, pattern generation, and STA constraints for testability.
• Perform post-silicon bring-up, debug, and instrument-level access troubleshooting.
• Collaborate with cross-functional leads to integrate DFT into design flows and tool methodologies.
• Mentor and lead a small team of DFT engineers; drive improvements to DFT methodologies and tools.

Requirements

Must-have technical skills, tools experience, and domain knowledge.

• Minimum ~10 years industry experience with at least ~8 years focused on DFT in custom ASIC design.
• Hands-on experience across DFT execution stages: SCAN, MBIST, validation, STA, IP-DFX, and post-silicon debug.
• Experience with DFT/test architecture for 2.5D/3D and chiplet designs.
• Strong fundamentals in digital and logic design, and proven problem-solving ability on complex designs.
• Proficiency with EDA tool flows (Siemens/Synopsys): Tessent, Spyglass/Tmax, Genus, Modus, NCSim/DC or equivalent.
• Proficiency with DFT languages and standards: ICL/PDL, PTAP/STAP, IEEE 1687; understanding of instrument-level access.
• Strong verification and debug skills for pre- and post-silicon validation.
• Effective written and verbal communication; ability to work across geographies and functions.
• Nice-to-have: scripting in Python, Perl, Tcl, C-Shell; experience improving DFT methodologies and automation.

Education Requirements

Bachelor's, Master's, or PhD in Computer Science, Electrical Engineering, or a related technical field is stated as the expected background. The posting specifies degrees (B.S./M.S./Ph.D.) in those fields and requests substantial industry experience (minimum 10 years).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.