Principal Engineer, DDEG Design Method

Job Title

Principal Engineer, DDEG Design Method

Role Summary

Lead verification and design-method efforts for full-chip gate-level and block-level DRAM and emerging memory designs, with emphasis on low-power and high-speed interfaces (DDR4/LPDDR4/DDR5/LPDDR5).

Work with international design and verification teams to develop verification methodology, automation, and flows that improve coverage and reduce debug time.

Experience Level

Senior-level engineer (principal-level).

Responsibilities

Primary responsibilities include verification leadership, developing automation and test infrastructure, and collaboration across design and verification teams.

• Leverage AI-based tools, agentic workflows, and automation frameworks to accelerate verification cycles, assist testbench/test-case generation, and improve debug efficiency.
• Validate AI outputs before use: review assumptions, align with specifications, cross-check with simulations and waveforms, and document decisions.
• Simulate, analyze, and debug pre-silicon block-level and full-chip designs; participate in silicon learning loops.
• Develop test cases, stimuli, testbenches, and test vectors to increase functional coverage for DRAM and emerging memory architectures.
• Run regressions and coverage analysis; drive verification improvements based on results.
• Participate in defining and evolving verification methodology and environments for advanced DRAM and emerging memory products, including low-power features.
• Collaborate with global teams and mentor junior engineers; provide technical guidance to the verification team.
• Use mixed-signal and digital simulation tools as required for verification and analysis.

Requirements

Must-have technical skills and competencies, followed by desirable skills.

• Must-have: Strong experience in SystemVerilog and UVM-based verification (SV testbenches, UVM testbench development).
• Must-have: Proven experience in digital and mixed-signal verification and proficiency with Verilog and SPICE or equivalent simulators.
• Must-have: Experience developing and maintaining testbenches, test vectors, running regressions, and performing coverage analysis.
• Must-have: Good communication and debugging skills; ability to work effectively in and lead teams.
• Must-have: Scripting skills (Python, Perl) for automation and verification infrastructure.
• Nice-to-have: Experience with DRAM, SRAM, or other memory design/verification.
• Nice-to-have: AMS verification and co-simulation experience; familiarity with tools such as Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, HSpice.
• Nice-to-have: Experience with PLI coding, Real Number Models, and other advanced verification utilities.

Education Requirements

Bachelor's or postgraduate degree in Electronics Engineering or a related engineering field is required.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.