Principal Engineer - Custom Layout (High-Speed Interface IP)

Job Title

Principal Engineer - Custom Layout (High-Speed Interface IP)

Role Summary

Lead physical implementation of advanced high-speed analog and mixed-signal IP blocks (DFE, CTLE, PLLs, CDRs, transmitters/receivers, SerDes) for interface products. Responsible for layout design, floorplanning, optimization, verification and signoff.

Provide technical leadership and mentor a small team while collaborating with Analog, Digital, SI, Packaging and Product teams to deliver silicon-proven designs in advanced process nodes.

Experience Level

Senior level — typically 15+ years of custom layout experience.

Responsibilities

The role focuses on end-to-end custom layout delivery and technical leadership.

• Lead custom layout development from floorplanning through tapeout for analog and mixed-signal IP.
• Implement critical blocks such as rCTLE, DFE, PLL, CDR, DLL and SerDes transmitters/receivers.
• Define floorplanning strategies to meet aggressive performance, area, power and yield targets.
• Perform transistor-level, device matching-aware layouts and high-speed signal routing.
• Drive physical verification and signoff activities: DRC, LVS, ERC, PERC, density checks and EMIR/parasitic analysis.
• Collaborate with Analog Design, Digital Design, SI, Packaging and Product Engineering teams during design, bring-up and qualification.
• Support silicon bring-up, debug, characterization and production qualification activities.
• Develop and institutionalize layout methodologies and mentor 3–4 junior layout engineers.

Requirements

Must-have skills and experience.

• 15+ years of industry experience in custom layout design for analog and mixed-signal circuits.
• Extensive experience in custom layout in advanced CMOS technologies; experience with 5nm and 3nm is emphasized.
• Strong understanding of analog layout fundamentals, device matching techniques, noise coupling mechanisms, parasitic extraction and optimization, and manufacturing process variations.
• Proven track record of delivering silicon-proven designs in advanced nodes.
• Experience with physical verification and signoff flows (DRC, LVS, PERC, EMIR, density verification).
• Ability to lead complex projects independently and to mentor a small team.

Nice-to-have:

• Hands-on experience with SerDes subsystems and high-speed interface IPs (DFE, CTLE, CDR, PLL, CDR).
• Experience with silicon bring-up, debug and production qualification.
• Experience developing and rolling out layout methodologies across an organization.

Education Requirements

B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, VLSI Design, or a related discipline from a reputed university. The posting also references Bachelor's or Master's degrees as the expected academic background.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.