Principal Engineer - ASIC Physical Design

Job Title

Principal Engineer - ASIC Physical Design

Role Summary

Senior physical design engineer responsible for block- and full-chip implementation of ASICs for Enterprise SSD products. Work includes floorplanning, placement, clock-tree synthesis, routing, RC extraction, timing closure, IR/EM analysis, physical verification, and tape-out activities.

Position requires leading implementation efforts, driving APR flow development and PPA analysis, and coordinating deliverables for subsystem partitions within a design team.

Experience Level

Senior — requires extensive hands-on experience. The posting specifies a minimum of 15 years of physical design/IR/EM experience.

Responsibilities

Primary responsibilities include implementation, verification, and leadership tasks to achieve tape-out-quality designs.

• Lead block and full-chip physical implementation: floorplanning, placement, CTS, routing, and RC extraction.
• Perform static timing analysis (STA) and drive timing closure at block and full-chip levels.
• Analyze and resolve IR/EM issues across block and full-chip designs.
• Execute physical verification and closure (DRC, LVS, antenna) and support signoff flows.
• Develop and improve APR flows and perform PPA (power, performance, area) analysis.
• Collaborate with architecture, RTL, verification, and system teams to meet deliverables and tape-out schedules.
• Manage and mentor team members responsible for subsystem partition closure and handoffs.

Requirements

Must-have technical skills, tools experience, and professional capabilities.

• Minimum 15 years hands-on physical design implementation, IR/EM analysis, and APR flow experience.
• Proven STA closure experience at block and full-chip levels.
• Experience with advanced process nodes; 5nm/3nm proficiency preferred.
• Experience using Ansys Redhawk-SC for power/IR/EM analysis.
• Hands-on experience with Cadence place-and-route and timing tools (Innovus, Tempus, or similar).
• Experience with physical verification tools such as Calibre for DRC/LVS/antenna closure.
• Strong fundamentals in digital electronics and microprocessor architectures; excellent analytical and problem-solving skills.
• Demonstrated ability to independently manage team deliverables, ownership, and time management.
• Required soft skills: professional English communication, collaboration, and interpersonal skills.
• Nice-to-have: Cadence PnR tool expertise beyond Innovus/Tempus, formal verification experience, strong verbal communication.

Education Requirements

Bachelor's or Master's degree in Electronics, Computer Engineering, Computer Architecture, or a related technical field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.