Principal Engineer, ASIC Analog Design

Job Title

Principal Engineer, ASIC Analog Design

Role Summary

Member of a high-speed PHY analog design team delivering analog/mixed-signal IP for advanced process nodes. Own analog sub-blocks through specification, circuit design, simulation, layout coordination, mixed-mode verification, and silicon correlation while working with global cross-functional teams.

Experience Level

Senior; requires 8+ years of relevant industry experience.

Responsibilities

Primary duties include architecture, design, verification, and delivery of analog PHY IP and supporting silicon validation.

• Own design, simulation, and mixed-mode verification of analog sub-blocks (PLL, DLL, CDR, RX/TX, high-speed datapath).
• Define block-level specifications and link budgets; create behavioral models, Verilog-A, timing views, and abstracts.
• Drive layout implementation and coordinate with mask/layout designers to meet process rules and DFM requirements.
• Lead silicon bring-up, characterization, and correlate silicon results with models and simulations.
• Collaborate with Packaging, Board, and cross-functional teams across locations to ensure system integration.
• Participate in design reviews; explain design choices and ensure robustness to internal teams and customers.
• Mentor and guide junior engineers and improve team productivity, including use of AI-enabled tools where appropriate.

Requirements

Must-have skills listed first; additional desirable skills noted under "Nice-to-have."

• Must-have: Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm–28nm), with hands-on FinFET experience (10nm and below).
• Must-have: Experience with high-speed memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) and/or SerDes interfaces (PCIe, MIPI, HDMI, USB, SATA).
• Must-have: Full ownership experience of at least one critical PHY sub-block (PLL, DLL, CDR, high-speed receiver with equalization, transmitter front-end, or high-speed data path).
• Must-have: Mandatory experience with SerDes and/or parallel interfaces and TX/RX equalization techniques (FFE, CTLE, DFE); experience with CDR and clocking architectures.
• Must-have: System-level modeling using Verilog-A and/or Python; ability to develop block specifications from link budgets.
• Must-have: Hands-on experience with tools such as Cadence ADE/Spectre/AMS verification, EM/IR flows, MATLAB, and Calibre.
• Must-have: Experience in lab testing, silicon bring-up, validation data analysis, and correlation of silicon with models.
• Nice-to-have: Experience working with Packaging and Board teams; knowledge of ESD design considerations, power delivery circuits (Bandgap, LDO, Bias), signal integrity, mismatch and Monte Carlo analysis, and transistor-level noise analysis.

Education Requirements

M.S./M.Tech or B.S./B.E. in Electronics.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.