Principal Engineer, ASIC Analog Design

Job Title

Principal Engineer, ASIC Analog Design

Role Summary

Lead analog/mixed-signal design for high-speed PHY IP on advanced process nodes, focusing on specification, circuit design, verification, layout coordination, silicon bring-up, and correlation.

Work within a global PHY design team to deliver robust analog sub-blocks for memory and SerDes interfaces used in high-performance products.

Experience Level

Senior-level — requires 8+ years of relevant industry experience working on analog/mixed-signal ASIC or IP design.

Responsibilities

Primary responsibilities include ownership of analog sub-blocks, design verification, and cross-functional collaboration.

• Design and simulate analog/mixed-signal blocks for high-speed PHYs targeting advanced nodes (12nm and below).
• Own block-level specifications, circuit implementation, mixed-mode verification, and reliability analysis for assigned sub-blocks.
• Drive layout implementation with mask/layout teams, ensuring process-rule and DFM compliance.
• Develop IP EDA views: behavioral models, Verilog-A, timing views, and abstracts.
• Participate in design reviews with internal teams and external customers; explain and defend design choices and robustness.
• Support silicon bring-up and characterization; correlate silicon results with models and simulations.
• Collaborate with packaging, board, and validation teams for system integration and testing.
• Mentor and guide junior engineers.

Requirements

Must-have technical skills and experience for the role. Items below were extracted from the posting; education details are summarized separately in the Education Requirements section.

• Strong analog/mixed-signal CMOS circuit design experience in deep sub-micron technologies (2nm to 28nm).
• Experience with high-speed memory interfaces (DDR3/4/5, LPDDR5/6, GDDR5/6/7) and/or SerDes interfaces (PCIe, MIPI, HDMI, USB, SATA).
• Full ownership experience of at least one critical PHY sub-block (examples: PLL, DLL, CDR, high-speed receiver with equalization, transmitter front-end, high-speed data path).
• Mandatory experience with SerDes and/or parallel interfaces and with TX/RX equalization techniques (FFE, CTLE, DFE).
• Experience with CDR and clocking architectures.
• Hands-on experience in FinFET technologies (10nm and below).
• Ability to develop block-level specifications using link budgets and system constraints.
• System-level modeling experience using Verilog-A and/or Python; working knowledge of mixed-mode simulation and signal integrity analysis.
• Experience in lab testing, silicon characterization, and validation data analysis.
• Experience designing high-speed I/O cells (DDR, LVDS, HSTL, CML) and power-delivery circuits (bandgap, LDO, bias).
• Knowledge of ESD design considerations, mismatch analysis, Monte Carlo, transistor-level noise analysis, and device physics.
• Experience supervising complex analog layouts and defining IP floorplans; familiarity with EM/IR flows.
• Hands-on with industry tools such as Cadence ADE, Spectre, AMS verification, MATLAB, and Calibre.

Nice-to-have:

• Experience leveraging AI-enabled tools to improve productivity.

Education Requirements

M.S./M.Tech or B.S./B.E. in Electronics. (The posting specifies 8+ years of experience in addition to the degree requirement.)

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.