Principal Engineer - Analog and Mixed-Signal Physical Design

Job Title

Principal Engineer - Analog and Mixed-Signal Physical Design

Role Summary

Hands-on Principal-level contributor responsible for physical implementation, timing closure, physical verification readiness, and custom IP integration for analog and mixed-signal silicon IP. Works within Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) to support cloud infrastructure and silicon development.

Role requires direct execution of Fusion Compiler-based APR flows, coordination with analog/layout teams, and cross-functional leadership while remaining technically engaged on critical implementation and closure tasks. Position expects an on-site cadence of approximately 3 days per week.

Experience Level

Senior / Principal-level. Typical experience: 8+ years of technical engineering experience; preferred 10+ years for some candidates. This is a senior individual contributor role.

Responsibilities

Primary delivery and technical leadership responsibilities include:

• Drive hands-on physical implementation for analog and mixed-signal IP: floorplanning, placement, routing, optimization, ECOs, and closure debug.
• Execute and own Fusion Compiler-based APR flows and implementation quality through signoff.
• Perform timing analysis and closure activities, including constraint review, timing debug, and ECO strategy.
• Partner with custom layout engineers to ensure integration feasibility, extraction, and physical verification closure.
• Debug complex implementation issues related to extraction, physical verification, reliability, and release readiness.
• Coordinate across architecture, circuit design, layout, CAD/methodology, verification, product engineering, and silicon integration stakeholders.
• Provide Principal-level technical leadership and mentorship while remaining directly engaged in execution.

Requirements

Must-have technical capabilities and expectations:

• Proven, hands-on experience implementing analog and mixed-signal physical design and integration for silicon IP.
• Deep expertise with Fusion Compiler-based APR and physical implementation flows (floorplan, placement, CTC, routing, optimization, ECOs).
• Strong timing closure skills, timing debug, and experience driving signoff readiness.
• Working understanding of custom analog layout integration, physical verification, and extraction considerations (sufficient to partner effectively with layout teams).
• Advanced debugging, analytical problem solving, and cross-functional communication skills.
• Track record of leading/mentoring engineers and coordinating cross-functional or distributed teams while remaining hands-on.
• Must be able to meet Microsoft security screening requirements (Microsoft Cloud Background Check) and satisfy applicable export-control eligibility checks.

Nice-to-have:

• Experience with PrimeTime timing analysis and constraint debug.
• Familiarity with Virtuoso-based custom layout methodologies and advanced-node implementation challenges.
• Hands-on tapeout or equivalent end-to-end silicon development experience.
• Experience coordinating external/V-team or vendor resources.

Education Requirements

Doctorate in EE/CE/CS or related field (with 3+ years experience), OR Master's in EE/CE/CS or related (with 6+ years), OR Bachelor's in EE/CE/CS or related (with 8+ years), OR equivalent practical experience. Fields mentioned: Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.