Principal Engineer, AMS IP Architecture

Job Title

Principal Engineer, AMS IP Architecture

Role Summary

Define and drive analog and mixed-signal (AMS) IP architectures, signal-processing algorithms, and calibration techniques to meet performance, power, and area targets for Intel products. Work within the architecture and engineering organization to deliver scalable, high-performance AMS IPs across multiple applications.

Experience Level

Senior / Principal level. Title indicates senior responsibility and technical leadership; typically aligned with 7+ years of relevant industry experience.

Responsibilities

Key responsibilities include:

• Architect end-to-end SerDes behavioral and link models (NRZ/PAM4) using MATLAB/Simulink.
• Execute sign-off link simulations (e.g., 100+ Gb/s per lane) to validate protocol compliance and margin before tapeout.
• Design real-time calibration and adaptation DSP algorithms that balance convergence, stability, and power.
• Correlate and validate simulation models against silicon measurements; iterate models to close gaps.
• Collaborate with analog, digital, and hardware teams on circuit trade-offs, logic design, and lab bring‑up.
• Perform link budget analyses and resolve technical field issues for client channel/module configurations.
• Review early-stage protocol updates and design specifications for system-level feasibility.

Requirements

Required and preferred technical qualifications.

• Must-have: Deep expertise in SerDes modeling (MATLAB/Simulink) or high-speed analog CMOS design; proven experience analyzing link budgets for NRZ or PAM4 signaling at 100Gb/s or higher, accounting for transmitter impairments, channel loss, reflections, crosstalk, and receiver noise.
• Must-have: Hands-on experience with transmitter/receiver architectures and equalization techniques (FFE, DFE, CTLE), CDR loop dynamics, and jitter tolerance; demonstrated ability to correlate models with silicon measurements and debug discrepancies.
• Must-have: Experience executing link-level sign-off simulations and mitigating margin risks prior to tapeout.
• Nice-to-have: Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping; DSP algorithm development experience.
• Must consent to and pass an extended Background Investigation (Position of Trust).

Education Requirements

M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with focus on high-speed communications, analog circuits, or signal processing.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.