Principal DV Engineer

Job Title

Principal DV Engineer

Role Summary

Lead verification of custom ASICs used in satellite and wireless telephony systems. You will develop and maintain SystemVerilog/Verilog UVM environments, execute verification plans, debug RTL and gate-level simulations, and drive coverage closure through chip tapeout.

This role is on-site in Saratoga, CA and involves technical leadership and coordination with design, firmware, and tapeout teams.

Experience Level

Senior — 10+ years of design verification experience in the semiconductor industry.

Responsibilities

Primary responsibilities for the Principal DV Engineer include designing verification infrastructure, executing verification campaigns, and leading closure activities through tapeout.

• Design and implement UVM-based verification environments and testbenches from scratch.
• Develop and maintain comprehensive test plans and test suites for ASIC blocks and full-chip integration.
• Write verification code in SystemVerilog/Verilog and support VHDL where needed.
• Use C/C++ where applicable for verification components and verification models.
• Automate verification flows with Python/Perl and bash scripting.
• Debug complex RTL simulations and gate-level simulations with SDF back-annotation; assess timing violations.
• Lead code and coverage-closure efforts and coordinate verification through chip tapeout.
• Mentor and guide other verification engineers and collaborate with design and firmware teams.

Requirements

Must-have technical skills and experience.

• Expert-level proficiency in Verilog and SystemVerilog.
• Proven experience building and maintaining UVM verification environments from scratch.
• Strong C/C++ skills for verification purposes.
• Proficient scripting in Python or Perl and comfortable with bash for automation.
• Experience writing test plans and maintaining test suites; strong simulation and debug skills.
• Experience debugging gate-level simulations with SDF back-annotation and evaluating timing violations.
• Proven track record leading coverage closure and driving verification through tapeout.
• 10+ years of semiconductor design verification experience.

Nice-to-have:

• VHDL experience.
• Familiarity with AI-assisted verification tools and workflows.
• Experience with satellite, wireless telephony, or mixed-signal ASICs.

Education Requirements

Not specified.

About the Company

Company: E-Space

Headquarters: Saratoga, CA, United States

E-Space develops low Earth orbit (LEO) satellite systems to enable hyper-scaled Internet of Things (IoT) connectivity. The company designs advanced satellite hardware and communication systems to reduce costs, improve scalability, and deliver actionable intelligence from space.