Principal DRAM Architect – GPU Memory Solutions

Job Title

Principal DRAM Architect – GPU Memory Solutions

Role Summary

Define and deliver architecture, roadmap, and implementation of next-generation DRAM and GPU memory solutions. Collaborate across I/O design, advanced packaging, process technology, DRAM vendors, and standards bodies to optimize performance, efficiency, and reliability.

Position sits on the Memory Architecture team and influences HBM, GDDR, LPDDR, and system-level memory trade-offs across AI, graphics, data center, and automotive platforms.

Experience Level

Senior — 15+ years in DRAM or memory system architecture, including at least 5+ years focused on HBM.

Responsibilities

Primary responsibilities include:

• Architect next-generation DRAM solutions: bank and stack structures, refresh/retention schemes, ECC/CRC, power management, and reliability optimizations.
• Lead high-speed memory interface innovation with expertise in HBM PHYs, timing margins, SI/PI, and PHY architecture considerations for GDDR/LPDDR.
• Collaborate on advanced packaging (TSVs, interposers, CoWoS, hybrid bonding, FOWLP) to co-optimize DRAM–GPU integration for bandwidth, power, thermal performance, and yield.
• Evaluate emerging DRAM process nodes and materials for impact on density, power, retention, and cost.
• Model and quantify system-level trade-offs across bandwidth, latency, power, cost, yield, and thermal behavior to guide architecture decisions.
• Work with DRAM vendors and standards bodies to influence roadmaps and contribute to JEDEC or equivalent committees.
• Mentor engineers, lead technical reviews, and drive long-term memory architecture direction.

Requirements

Must-have qualifications:

• 15+ years of experience in DRAM or memory system architecture, with at least 5+ years focused on HBM (HBM2/2e/3/3e or next-gen).
• Proven expertise in HBM architecture: TSV design, die stacking, interposer/CoWoS integration, refresh schemes, ECC/CRC, pseudo-channels, and thermal/power management.
• Participation in JEDEC or equivalent standards organizations, contributing to DRAM or HBM specifications.
• Proven ability to influence DRAM vendor roadmaps and enable early silicon validation.
• Strong understanding of I/O and PHY fundamentals — timing, SI/PI, equalization, and jitter budgeting.
• Experience balancing system-level trade-offs across performance, bandwidth, power, cost, yield, and reliability.
• Exceptional technical leadership and cross-functional communication skills.

Nice-to-have:

• Hands-on experience with GDDR6/7 and LPDDR5/6 architectures.
• Deep understanding of thermal and mechanical challenges in advanced memory packaging and 3D integration.
• Familiarity with emerging memory technologies (3D DRAM, MRAM, RRAM, hybrid memory).
• Publications, patents, or leadership roles demonstrating influence on memory architecture and standards.
• Background in high-bandwidth computing platforms (AI, HPC, graphics accelerators).

Education Requirements

MS or PhD in Electrical Engineering, Computer Engineering, Physics, or equivalent practical experience.

About the Company

Company: NVIDIA

Headquarters: Santa Clara, California, USA

NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.