Principal Digital Verification Engineer (m/f/d)

Job Title

Principal Digital Verification Engineer (m/f/d)

Role Summary

Lead verification activities for one or more digital submodules, owning verification IPs, testbenches and the verification strategy for assigned scope. Work with subsystem architects, HW/SW designers and the DV team to plan, execute and close verification campaigns against requirements.

Define metrics, track coverage and verification progress, document results, and contribute to DV process and methodology improvements.

Experience Level

Senior — requires significant experience; the role specifies at least eight years of professional experience in Digital Design and Verification.

Responsibilities

Primary duties include ownership of verification scope, planning and collaboration with architects and leads, and reporting of verification status and metrics.

• Take ownership of verification for assigned submodules, including verification IPs and testbenches at multiple integration levels.
• Review and analyze subsystem/submodule requirements and design specifications for each functional or technology increment.
• Collaborate with subsystem architects and discipline leads to define an integrated verification strategy and break it down into tasks.
• Define and document metrics and methodologies to assess verification completion; specify testbench components as required.
• Track and document verification activities, update verification specifications and reports at project reviews.
• Work with peers, HW/SW designers and system engineers to analyze and resolve issues, bugs and support requests.
• Contribute to maintenance and improvement of the digital verification process and team methodology.
• Keep current with verification methodologies and tools through courses and technical literature.

Requirements

Essential technical skills, tools experience and professional behaviours required for successful performance in this role.

• Minimum eight years of professional experience in digital design and verification.
• Proven experience in testbench design and development using UVM methodology.
• Advanced knowledge of Verilog and SystemVerilog; VHDL is a plus.
• Strong competence in metric-driven verification, functional and code coverage.
• Experience with directed and constrained-random verification methodologies.
• Advanced knowledge of formal verification methodologies and assertions.
• Familiarity with ASIC/SoC design flow and process.
• Proficiency in scripting and test-case languages: bash/tcsh, tcl, Python and C.
• Experience with centralized version control systems (e.g. SVN, GIT, Clearcase).
• Comfortable working in a collaborative, technically demanding team; strong written and spoken English.
• May be assigned security-related tasks that require disciplined, reliable handling and could be subject to security certification scope.
• Nice-to-have: formal training certifications in SystemVerilog/UVM from EDA vendors; VHDL experience.

Education Requirements

University degree (Master's or PhD) in Electrical/Electronic Engineering, Computer Science or equivalent, or equivalent practical experience. SystemVerilog and UVM methodology training certifications from EDA vendors are explicitly mentioned.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.