Principal Digital Methodology Engineer - Design for Testability (DFT)

Job Title

Principal Digital Methodology Engineer - Design for Testability (DFT)

Role Summary

Lead development and deployment of DFT methodologies and test architectures for large-scale ASIC and SoC programs. Work within the Digital Methodology Center of Excellence to define best practices, automation, and customer-facing methodology packages that ensure manufacturable, high-coverage designs.

Collaborate with R&D, product engineering, and strategic accounts to translate deployment challenges into product requirements and to drive adoption of standards-based test architectures.

Experience Level

Senior - typically requires 15+ years in the semiconductor or EDA industry, with at least 5 years focused on DFT architecture, ATPG, and manufacturing test methodologies.

Responsibilities

Primary responsibilities include defining methodology, deploying test solutions, and leading technical customer engagements.

• Define and drive DFT methodologies for next-generation ASIC and SoC designs across strategic customer programs.
• Lead deployment of scan compression, hierarchical DFT, IEEE 1500 wrappers, IJTAG instrumentation, and embedded test IP.
• Architect scalable test access infrastructures using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 for multi-die and chiplet systems.
• Develop automation frameworks, signoff criteria, and reusable methodology packages using Tcl, Python, and Perl.
• Serve as technical SME for Synopsys TestMAX DFT, TestMAX ATPG, diagnosis, and silicon lifecycle solutions in customer engagements.
• Collaborate with R&D to influence TestMAX product roadmap based on deployment challenges and customer requirements.
• Provide technical leadership for methodology reviews and complex DFT architecture decisions that impact tapeout schedules.

Requirements

Must-have technical skills and experience; nice-to-have items noted.

• Must-have: 15+ years in semiconductor or EDA and 5+ years focused on DFT architecture, ATPG, and manufacturing test methodologies.
• Must-have: Proven experience architecting and implementing DFT solutions for large-scale ASIC/SoC designs, including successful tapeouts.
• Must-have: Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG in production design environments.
• Must-have: Deep technical knowledge of scan insertion, scan compression, hierarchical DFT, ATPG and diagnosis, and coverage optimization; familiarity with stuck-at, transition, path-delay, bridge and cell-aware fault models.
• Must-have: Experience deploying IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards in complex test access architectures.
• Must-have: Proficiency with Tcl, Python, Perl, or Shell scripting for methodology automation.
• Must-have: Strong understanding of RTL-to-GDSII flows and how DFT interacts with synthesis, physical design, timing closure, and signoff.
• Nice-to-have: Background with advanced-node ASICs, multi-billion-gate SoCs, silicon bring-up, diagnosis, or yield improvement; knowledge of functional safety and automotive test requirements.
• Nice-to-have: Contributions to industry test standards, technical publications, patents, or conference presentations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.