Principal Digital Implementation Engineer

Job Title

Principal Digital Implementation Engineer

Role Summary

Senior hands-on RTL engineer in the Performance Solutions Group (PSG) working on complex, high-performance SoC and subsystem designs. The role spans microarchitecture, RTL implementation, verification collaboration, synthesis, and handoff to physical implementation teams.

Work involves designing synthesizable SystemVerilog RTL, integrating IP, and resolving cross-domain implementation issues to deliver silicon-quality designs.

Experience Level

Senior — typically requires 10+ years of RTL/ASIC design experience.

Responsibilities

Primary responsibilities include design, verification collaboration, and integration of synthesizable RTL for advanced SoCs.

• Design, implement, and integrate synthesizable RTL using SystemVerilog.
• Translate architectural specifications into efficient microarchitectures and RTL.
• Develop and maintain unit- and block-level test environments with verification engineers.
• Debug functional issues using simulation, waveform analysis, assertions, and verification tools.
• Support synthesis, timing analysis, linting, CDC analysis, and other front-end quality checks.
• Collaborate with physical design teams on timing, power, area, and implementation constraints.
• Integrate internally developed and third-party IP and troubleshoot integration issues.
• Document interfaces, microarchitecture, and implementation details in the team's QMS.
• Contribute to RTL methodology, automation, and continuous improvement efforts.

Requirements

Must-have technical skills and experience.

• Proficiency in Verilog/SystemVerilog and experience producing synthesizable RTL for ASIC or FPGA.
• Strong understanding of digital synchronous design, control logic, datapaths, and memory interfaces.
• Experience with simulation, RTL debugging, assertions, and formal verification techniques.
• Familiarity with common SoC interfaces and protocols (for example AMBA/AXI, AHB, APB).
• Working knowledge of synthesis, timing closure considerations, static analysis, lint, and CDC.
• Experience with performance, power, and area optimization and RTL-to-gates implementation flows.
• Strong problem-solving skills and ability to work effectively within multidisciplinary teams and with customers.

Nice-to-have:

• Background in CPU, GPU, AI/ML, networking, or other high-performance compute architectures.
• Experience with low-power design techniques and high-speed interface implementations.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.