Principal Digital IC Design Engineer

Job Title

Principal Digital IC Design Engineer

Role Summary

Lead technical authority for full-flow ASIC/SoC development, owning projects from system architecture and RTL through physical sign-off and silicon bring-up. The role bridges architecture, RTL design, verification, and physical implementation to deliver commercial tape-outs.

Experience Level

Senior - Principal level; typically requires 12+ years of hands-on digital ASIC design and implementation experience.

Responsibilities

Primary responsibilities span technical leadership, front-end microarchitecture, and back-end physical implementation.

• Define and improve ASIC design methodologies and full-flow architectures across teams.
• Act as chief technical authority aligning Architecture, RTL Design, Verification, and Physical Design teams.
• Evaluate and make trade-offs for Power, Performance, and Area (PPA).
• Translate system requirements into SoC/ASIC microarchitecture and RTL.
• Write scalable, synthesizable SystemVerilog/Verilog code and review DV test plans; implement DFT strategies.
• Drive synthesis, floorplanning, clock tree synthesis, Place & Route, and full-chip sign-off flows.
• Define timing constraints, perform deep STA, and resolve setup/hold and other timing issues.
• Oversee physical verification (DRC, LVS, ERC) to ensure tape-out readiness.
• Lead silicon bring-up, hardware debug, and lab validation activities.
• Mentor senior and mid-level engineers and communicate complex technical issues to stakeholders.

Requirements

Must-have technical skills and demonstrated experience.

• 12+ years of direct industry experience in digital ASIC design and implementation, with multiple successful commercial tape-outs.
• Expertise in SystemVerilog and Verilog.
• Proven, hands-on RTL-to-GDSII full-flow implementation: logic synthesis, floorplanning, CTS, P&R, STA, and physical verification.
• Deep proficiency with Synopsys or Cadence flagship EDA toolchains (examples: Design Compiler, IC Compiler II, PrimeTime; Genus, Innovus, Tempus).
• Scripting and automation skills in Python, TCL, and shell (Bash/Perl) for methodology customization and CAD data manipulation.
• Direct experience with silicon bring-up, hardware debugging, and lab evaluation.
• Strong mentorship, leadership, and verbal/written communication skills.
• Nice-to-have: prior experience with Power Management ICs.

Education Requirements

Required: Bachelor's degree in Electrical Engineering. Preferred: Master's or PhD in Electrical Engineering. The posting allows equivalent practical industry experience in lieu of additional formal education (source states "12+ years of experience or equivalent amount of advanced education and experience").

About the Company

Company: Qorvo

Headquarters: Greensboro, NC, US

Qorvo supplies innovative semiconductor solutions that enhance connectivity and power for a variety of applications, including consumer electronics, automotive, and healthcare. With a focus on RF and power solutions, Qorvo combines technology leadership and global manufacturing to address complex challenges in fast-growing industries. Their commitment to excellence and innovation drives them to shape the future of wireless communications.