Principal Digital Design Engineer / Chip Lead

Job Title

Principal Digital Design Engineer / Chip Lead

Role Summary

Lead digital design and chip integration for high-speed interface/PHY-adjacent silicon across architecture, RTL, synthesis, timing closure, verification coordination, and tape-out. Work on a small senior team focused on delivering novel PHY solutions to silicon.

Experience Level

Senior — requires substantial experience; the role expects 10+ years of ASIC/digital design experience with prior tape-out experience in a lead or senior designer role.

Responsibilities

Drive chip-level digital design, integration, and delivery from architecture through tape-out.

• Define top-level chip architecture and partitioning between hard macros and soft IP.
• Author, review, and maintain synthesizable RTL (SystemVerilog) for control blocks, CSR/register files, clocking control, and top-level integration.
• Develop and own chip-level timing constraints (SDC), CDC strategy, and per-block timing budgets.
• Lead synthesis and optimization efforts (Design Compiler / Genus) to meet PPA targets.
• Coordinate with DV teams on assertion-, coverage-, and formal-driven verification; define verification plans and review coverage metrics.
• Manage IP integration: interfaces between PHY hard macros, third-party soft IP, and internal blocks; coordinate with vendors.
• Own tape-out readiness and sign-off processes, coordinating with physical design, verification, and analog teams.
• Produce architecture and block-level specifications and capture design decisions for follow-on development.

Requirements

Must-have:

• 10+ years of ASIC/digital design experience with at least one prior tape-out in a chip lead, design lead, or senior designer role.
• Expert-level SystemVerilog RTL design and coding best practices.
• Strong experience with logic synthesis tools (Synopsys Design Compiler or Cadence Genus) and static timing analysis (PrimeTime or Tempus).
• Proficiency with RTL simulation and debug tools (VCS, Xcelium, or equivalent; Verdi or DVE for waveform debug).
• Solid understanding of CDC analysis methodologies and tools (SpyGlass, JasperGold CDC, or equivalent).
• Demonstrated experience integrating hard and soft IP in mixed-signal or PHY-adjacent chips.
• Proven ability to lead technically on a small team and own deliverables under incomplete information.
• Strong written communication skills for producing specifications and design documentation.
• Experience partnering with design verification teams to define plans, review coverage, and close functional and corner cases before tape-out.
• Proficiency in leveraging AI tools to improve engineering productivity.

Nice-to-have:

• Experience with high-speed PHY architectures (SerDes, DDR, or equivalent analog I/O).
• Familiarity with I2C management bus, Eye Monitor control logic, or PRBS-based error counting.
• Experience defining DFT strategy (scan insertion, ATPG planning, boundary scan for high-speed I/O).
• Familiarity with OTP/fuse-based trim and calibration for PHY analog parameters.
• Prior experience in small-team or startup-like environments.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.