Principal Digital Design Engineer / Chip Lead

Job Title

Principal Digital Design Engineer / Chip Lead

Role Summary

Lead a small technical team on the Interface Pathfinding organization to define top-level chip architecture, integrate hard and soft IP, and deliver high-speed interface solutions for memory and storage used in AI/ML and advanced computing systems. Responsible for architecture, RTL development, timing closure, synthesis optimization, verification coordination, and tape-out readiness.

Experience Level

Senior — requires 10+ years of ASIC/digital design experience with at least one prior tape-out in a leadership role.

Responsibilities

Key responsibilities include chip-level architecture, RTL implementation, timing, synthesis, IP integration, and delivery of tape-out quality designs.

• Define top-level chip architecture and manage integration of hard and soft IP blocks.
• Author, review, and maintain synthesizable SystemVerilog RTL for control blocks and top-level integration.
• Develop and own chip-level timing constraints and clock-domain crossing strategies.
• Drive logic synthesis and optimize for performance, power, and area (PPA).
• Coordinate with design verification teams to define verification plans and ensure quality verification of control logic and system behavior.
• Manage IP integration agreements and coordinate with PHY hard-macro and soft-IP vendors.
• Oversee tape-out checklist and sign-off processes for foundry handoff.
• Create and maintain architecture specifications and authoritative design documentation.
• Capture design decisions and lessons learned to improve future chip development.

Requirements

Must-have technical skills and experience.

• 10+ years of ASIC/digital design experience with leadership responsibility on at least one tape-out.
• Expert-level SystemVerilog RTL design and coding best practices.
• Strong experience with logic synthesis tools and static timing analysis for timing closure.
• Proficiency with RTL simulation and debug tools and methodologies.
• Solid understanding of clock-domain crossing (CDC) analysis and related tools.
• Demonstrated experience integrating hard and soft IP in PHY-adjacent or mixed-signal environments.
• Proven ability to lead a small technical team and make technical decisions toward tape-out.
• Strong written communication skills for specifications, design documentation, and vendor coordination.
• Experience partnering with verification teams to define verification scope and quality targets.
• Familiarity with leveraging AI tools to improve engineering productivity (preferred).

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.