Principal Digital Design Engineer

Job Title

Principal Digital Design Engineer

Role Summary

Technical leader responsible for defining and driving digital architecture for mixed-signal motor-drive SoCs and IP across a multi-site team. Lead architecture, RTL design, integration, verification strategy, and FPGA/pre-silicon validation to deliver robust automotive-grade silicon.

Work closely with physical implementation, systems, software, test, and external partners to resolve timing, power, area, and verification challenges.

Experience Level

Senior / Principal level. The role expects extensive, proven experience in senior or principal digital design positions; no specific years-of-experience were stated.

Responsibilities

Accountable for system-level digital architecture and delivery across IP and full SoC projects.

• Define system-level requirements and own digital architecture for IP and SoC solutions.
• Architect and implement reusable RTL modules and chip-top integration using Verilog, with focus on low-power and high-performance design.
• Drive digital design methodology improvements and evaluate new tools and best practices.
• Oversee FPGA validation, pre-silicon emulation, and ensure hardware/software interface integrity.
• Support and shape the verification strategy and functional coverage goals to achieve first-pass silicon success.
• Collaborate with physical implementation to address timing, power, and area trade-offs on advanced process nodes.
• Mentor and develop engineers across the digital design team.
• Lead technical interactions with customers, off-site design teams, EDA vendors, and IP providers.

Requirements

Must-have technical skills and responsibilities for successful execution.

• Expert-level knowledge of digital architectures from algorithmic IP to full SoC designs, including CPU subsystems and interconnect fabrics (e.g., AMBA/AXI).
• Proven track record leading complex digital architecture and integration through specification, tape-out, and silicon validation.
• Mastery of advanced digital design techniques, including low-power and high-speed design practices.
• Deep practical experience with DFT/DFM techniques such as scan compression, boundary scan, and memory BIST.
• Expertise in advanced FPGA prototyping and emulation for complex systems.
• Demonstrated ability to lead technical teams, make trade-offs, and mentor other engineers.
• Strong verbal and written communication skills for cross-functional and external technical engagements.
• Willingness to travel internationally and domestically as required (~5–10% each indicated).

Nice-to-have:

• Experience with Cadence or equivalent EDA toolsets for front-end design and verification flows.
• Experience with functional safety standards such as ISO 26262.

Education Requirements

Essential: PhD or Master’s degree (or equivalent practical experience) in Electronics or a related field. The posting explicitly allows equivalent experience in lieu of the stated degrees.

About the Company

Company: Allegro MicroSystems

Headquarters: Manchester, New Hampshire, USA

Global semiconductor company with over 30 years of innovation, developing semiconductor devices and design enablement tools. Allegro focuses on device development, foundry partnerships, IP characterization, and design automation to support product roadmaps and technology advancement.