Principal Die-to-Die Interconnect Modeling Architect

Job Title

Principal Die-to-Die Interconnect Modeling Architect

Role Summary

The Modeling Architect will lead a technical team to build and evolve behavioral and architectural models for die-to-die (D2D) physical layers, enabling predictive performance analysis and silicon correlation for high-speed interconnects.

Primary responsibilities include communication-theory-driven algorithm development, system-level modeling, adaptation algorithm modeling, and architectural verification across multidisciplinary engineering teams.

Experience Level

Senior level. Role expects 12–15+ years of related experience depending on degree (PhD +12 years or MS +15 years) and demonstrated leadership in architecture and modeling.

Responsibilities

Lead model development, verification, and cross-functional architecture activities to ensure model-to-silicon alignment.

• Develop behavioral and architectural system-level models (MATLAB, Python, SystemC or equivalent) covering transmitter, receiver, package, channel, clocking, equalization, adaptation, and protocol interactions.
• Predict link performance: BER, latency, throughput, bandwidth density, power, energy efficiency, and manufacturing margin.
• Perform statistical and Monte Carlo analyses and architectural sensitivity studies across PVT, aging, jitter, noise, and channel impairments.
• Drive algorithm verification of Verilog/RTL implementations and model-to-RTL correlation.
• Define architectural verification strategies, golden-reference models, validation methodologies, and success criteria.
• Correlate models with lab characterization and production silicon; identify gaps and recommend corrective actions.
• Provide technical leadership across architecture, analog/digital design, firmware, packaging, signal integrity, verification and product engineering; mentor engineers.

Requirements

Must-have technical skills and demonstrable experience; degree requirements are listed separately under Education Requirements.

• Deep knowledge of communication theory, equalization, adaptive algorithms, timing and margin budgeting, and error-term analysis.
• Experience with high-speed SerDes or die-to-die communication system architectures.
• Extensive experience developing behavioral and architectural models using MATLAB, Python, SystemC, or equivalent tools.
• Experience translating architecture models to RTL and driving architectural verification and silicon correlation.
• Proven ability to evaluate hardware tradeoffs (equalization, noise budgets, convergence, numerical stability) and assess implementation feasibility.
• Experience conducting Monte Carlo evaluations and statistical performance prediction.
• Strong cross-functional leadership and ability to drive architecture reviews and technical decisions.
• Preferred: experience with advanced packaging (interposers, EMIB, hybrid bonding, 3D integration) and prior management experience.

Education Requirements

MS in Electrical Engineering or Computer Engineering with 15+ years of related experience, or PhD in Electrical Engineering or Computer Engineering with 12+ years of related experience. Related technical fields or equivalent practical experience implied by the stated years-of-experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.