Principal DFT Engineer (Silicon Engineering)

Job Title

Principal DFT Engineer (Silicon Engineering)

Role Summary

Lead design-for-test (DFT) implementation and ATPG methodologies for next-generation ASICs used in space and ground infrastructure. Work with cross-disciplinary teams (architecture, RTL design, physical design, validation, firmware, and product engineering) to deliver DFT solutions from concept through tapeout and post-silicon validation.

Experience Level

Senior — requires significant experience; posting specifies 10+ years of ASIC and DFT experience.

Responsibilities

Primary responsibilities include design, implementation, verification, and support of DFT flows and tools:

• Design and optimize DFT architectures: scan insertion, compression/decompression, memory BIST, logic BIST.
• Develop and own ATPG methodologies and tools, generate patterns for stuck-at, transition, and path-delay models, and optimize pattern compression and diagnosis.
• Evaluate design readiness for scan insertion using RTL and physical design scan DRC checks.
• Integrate and verify DFT fabrics and IP within subsystems; support hierarchical test flows.
• Run and debug non-timing and SDF-annotated gate-level simulations; provide post-silicon test and validation support.
• Automate test flows and data analysis; develop test scripts and tooling.

Requirements

Must-have skills and constraints; preferred items listed after.

• 10+ years working with ASICs, including DFT setup, integration, and validation.
• Hands-on experience with scan insertion and DFT implementation using tools such as Siemens Tessent.
• Experience owning ATPG flows and pattern generation for multiple fault models; familiarity with pattern compression and diagnosis.
• Gate-level simulation and SDF-annotated simulation debug experience.
• Proficiency scripting and automating flows in languages such as Perl, Python, Tcl, or C/C++.
• Willingness to work extended hours and weekends to meet critical milestones.
• Must meet U.S. export-control/ITAR person eligibility (U.S. person as defined by ITAR).

Nice-to-have:

• Leadership experience driving SOC DFT from concept through tapeout and product deployment.
• RTL familiarity for tracing and debugging connectivity issues related to DFT; Verilog/SystemVerilog experience.
• Experience with UPF, formal verification, DRC rule checking, and ATE/test team interaction.
• Knowledge of advanced silicon process nodes, low-power design, and clock-domain crossing challenges.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science is required (per posting). No alternate degree or "equivalent experience" language was provided in the source.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.