Principal DFT Engineer (Silicon Engineering)

Job Title

Principal DFT Engineer (Silicon Engineering)

Role Summary

Lead DFT architecture, implementation, and validation for advanced ASICs used in SpaceX Starlink space and ground products. Work with cross-disciplinary teams (system, firmware, architecture, design, validation, product engineering, ASIC implementation) to deliver silicon from RTL through tapeout and post-silicon validation.

This role focuses on production-quality DFT and ATPG flows, scan infrastructure, memory and logic BIST, and post-silicon test/debug for high-reliability space and ground ASICs.

Experience Level

Senior — Principal level. Source lists 10+ years of ASIC and DFT experience and senior leadership expectations.

Responsibilities

Primary responsibilities include owning DFT implementation, ATPG methodology, and supporting silicon bring-up and validation.

• Lead design and optimization of DFT architectures: scan insertion, compression/decompression, memory BIST, logic BIST.
• Configure and run ATPG flows for stuck-at, transition, and path delay faults; focus on pattern compression, diagnosis, and hierarchical flows.
• Use Siemens Tessent (or equivalent) for RTL and gate-netlist DFT implementation and pattern generation.
• Evaluate design readiness for scan insertion and run Scan DRC checks across RTL and physical design flows.
• Integrate and verify DFT fabrics and IP within subsystems; run and debug non-timing and SDF-annotated gate-level simulations.
• Develop and maintain test automation and data-analysis scripts and tools (Perl, Python, Tcl, C/C++).
• Provide post-silicon testing, debugging, and validation support; collaborate with test engineering and ATE teams.

Requirements

Must-have technical skills and constraints for the role.

• 10+ years working with ASICs, with significant experience in scan insertion and DFT setup, integration, and validation.
• Hands-on experience with ATPG methodologies, pattern compression, diagnosis, and hierarchical test flows.
• Practical experience with Siemens Tessent or equivalent DFT toolset and gate-level simulation/debug.
• Strong RTL understanding to trace and debug connectivity issues related to DFT.
• Ability to write and maintain automation and analysis scripts (Perl, Python, Tcl, C/C++).
• Experience with clock domain crossings, power-related issues, and non-timing simulation debug.
• Willingness to work extended hours and weekends as required to meet critical milestones.
• Must meet ITAR eligibility requirements (U.S. citizen, U.S. lawful permanent resident, Refugee, Asylee, or eligible for required U.S. Department of State authorizations).

Nice-to-have:

• Experience leading SoC-level DFT from concept through tapeout and product deployment.
• Familiarity with UPF, formal verification, and DRC rule checking.
• Knowledge of advanced process nodes and high-speed / low-power silicon design considerations.
• Strong Verilog/SystemVerilog implementation experience and familiarity with ATE testers.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science is specified. The posting emphasizes significant practical ASIC/DFT experience (10+ years); no explicit mention of required advanced degrees or alternate-equivalent phrasing was provided.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.