Principal DFT Engineer

Job Title

Principal DFT Engineer

Role Summary

Lead DFT engineer responsible for designing and delivering design-for-test solutions for SoC/ASIC projects. Work with architecture, design, verification, and customer teams to implement scan, compression, LBIST/MBIST and ATPG flows and achieve production test coverage goals.

Experience Level

Senior — approximately 7–12 years of experience in SoC/ASIC digital design with a focus on DFT.

Responsibilities

The principal responsibilities include planning and executing DFT implementation, validating test infrastructure, and driving failure analysis to meet test targets.

• Lead DFT insertion and implementation for SoC/ASIC designs.
• Implement scan chain insertion using synthesis and related tools.
• Design and integrate compression scan insertion and LBIST.
• Develop and validate MBIST for memories.
• Create and run ATPG to meet fault-coverage objectives.
• Debug test failures, analyze root causes, and improve fault coverage.
• Verify ATPG testbenches and resolve simulation mis-compares.
• Collaborate with architecture, design, verification, and external customers to deliver DFT tasks independently.

Requirements

Must-have technical skills and experience, plus a few desirable qualifications.

• Must-have: 7–12 years of professional experience in SoC/ASIC digital design with a focus on DFT.
• Must-have: Intimate knowledge of DFT insertion flows and scan chain insertion techniques.
• Must-have: Experience with compression scan insertion, LBIST, and memory BIST (MBIST).
• Must-have: Expertise in Automatic Test Pattern Generation (ATPG) and achieving design test coverage goals.
• Must-have: Strong debugging and failure-analysis skills; experience verifying ATPG testbenches.
• Must-have: Working knowledge of JTAG (1149.1/6), IEEE1500 and IEEE1687.
• Must-have: Ability to work independently and collaborate across cross-functional teams.
• Nice-to-have: Prior experience with Cadence DFT tools and flows.
• Nice-to-have: Knowledge of timing analysis and equivalency checking.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.