Principal DFT Engineer

Job Title

Principal DFT Engineer

Role Summary

Lead end-to-end Design-for-Test (DFT) activities for complex automotive MCU/SoC products. Work across SoC design, verification, product and test teams to define DFT architecture, implement solutions, verify test modes, and deliver production-ready test patterns and debug support for silicon bring-up and production ramp.

Experience Level

Senior - typically requires 15+ years of experience in DFT architecture and implementation for complex MCU/SoC devices.

Responsibilities

Deliver DFT strategy, implementation, verification and production-test readiness for automotive MCU/SoC products.

• Define and own DFT architecture and strategy from spec to silicon production readiness.
• Specify and implement scan architecture, compression, memory BIST, logic BIST, boundary scan/JTAG and test access architecture.
• Drive DFT-related RTL/design updates and collaborate with SoC, IP and RTL design teams.
• Plan and execute DFT verification and simulation, including test-mode validation, scan/MBIST connectivity and gate-level verification.
• Lead ATPG, pattern generation, validation and release of production-ready test patterns to Product and Test Engineering.
• Interface with Product/Test Engineering on ATE, production-test requirements, silicon bring-up, pattern debug and yield investigations.
• Review coverage, pattern count and testability metrics; identify and close gaps; manage DFT deliverables, reviews and sign-offs.
• Identify technical and schedule risks related to DFT and drive cross-functional mitigation.

Requirements

Must-have technical skills and experience listed below. Preferred items follow.

Must-have

• 15+ years of hands-on experience in DFT architecture and implementation for complex MCU/SoC devices.
• Expertise in scan insertion, scan compression, ATPG, MBIST and JTAG/boundary scan.
• Strong understanding of RTL and gate-level design, clocks, resets, power domains and SoC integration.
• Experience with DFT simulation, pattern verification and gate-level simulation/debug.
• Experience in ATPG pattern generation, fault coverage analysis and production pattern delivery.
• Experience collaborating with Product Engineering and Test teams during silicon bring-up and production ramp.
• Familiarity with DFT tool flows from Siemens EDA, Synopsys and/or Cadence.
• Proven ability to lead DFT activities independently and communicate across architecture, design, verification and test organizations.

Nice-to-have

• Experience with automotive MCU or automotive SoC development.
• Exposure to ISO 26262 / functional safety and its impact on test architecture.
• Experience with hierarchical test, embedded compression, logic BIST, repair/redundancy schemes or safety-oriented test features.
• Understanding of production test cost, test time, diagnostics and yield considerations.

Education Requirements

Not specified.

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.