Principal Development Engineer (Virtual Solution)

Job Title

Principal Development Engineer (Virtual Solution)

Role Summary

The Principal Development Engineer will design and deliver system-level Accelerated Verification IP (AVIP) solutions for emulation and prototyping platforms to validate complex SoCs and subsystems. The role works with emulation/prototyping hardware, verification environments, tools and customers to enable scalable, high-performance system validation.

Experience Level

Senior — expects approximately 5–10 years of relevant experience.

Responsibilities

Key responsibilities include design, integration, and customer enablement for system-level verification on emulation/prototyping platforms.

• Design and develop system-level AVIP solutions for emulation/prototyping platforms (e.g., Palladium, Protium).
• Build and integrate accelerated verification IP environments for complex SoC and subsystem validation.
• Develop end-to-end verification flows: AVIP integration, testbench and system modeling, and bare-metal/driver-level validation.
• Architect scalable solutions for multi-protocol system validation across multiple clock domains.
• Optimize solutions for performance, scalability, and emulation efficiency.
• Create custom test cases, tools, and automation for embedded, co-emulation, and hybrid flows.
• Collaborate with product engineering, field application teams, and customers to debug and resolve system-level issues.
• Support customer bring-up, debug, and solution deployment.
• Contribute to AVIP methodology evolution, including integration with AI/ML-based verification flows.

Requirements

Must-have technical skills and experience; a separate list of desirable skills is provided.

• Must-have:
• 5–10 years of relevant industry experience in system verification or related fields.
• Expertise with at least one high-speed protocol such as PCIe, CXL, AMBA, UCIe, or Ethernet.
• Strong RTL design skills (SystemVerilog / Verilog).
• Proficient in C/C++ for modeling, testbench development, or system integration.
• Solid understanding of system-level verification methodologies and emulation/acceleration flows.
• Proven debugging skills for complex system integration issues.
• Excellent English communication (verbal and written).

• Nice-to-have:
• Hands-on experience with Palladium, Protium, FPGA, or other emulation/prototyping platforms.
• Experience developing or using AVIP solutions and end-to-end validation flows (simulation → emulation → prototyping).
• Knowledge of UVM, QEMU/Gem5, or similar system-emulation projects.
• Experience in multi-language environments (SystemVerilog + C/C++ + Python).
• Exposure to applying AI/ML techniques to verification or tooling.
• Ability to work independently and strong problem-solving skills.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (as listed in the qualifications).

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.