Principal Design Verification Engineer — High-Performance CPU Subsystem

Job Title

Principal Design Verification Engineer — High-Performance CPU Subsystem

Role Summary

Lead verification strategy and execution for a high-performance out-of-order CPU core and coherent interconnect/subsystem. Individual contributor role collaborating with architecture, RTL, formal, performance, and verification teams to ensure design correctness and signoff quality.

Focus areas include core microarchitecture behaviors, cache-coherent data movement, protocol correctness, and subsystem integration.

Experience Level

Senior — Principal level; requires 12+ years of relevant CPU/core or SoC functional verification experience.

Responsibilities

Key responsibilities include:

• Define and lead verification strategy for CPU cores and coherent interconnects from block-level to subsystem signoff.
• Plan, execute, and close verification: test development, coverage analysis, debug, and closure criteria.
• Develop checkers, scoreboards, assertions, stimulus, and coverage models to expose corner cases and improve bug-finding efficiency.
• Select and apply simulation, formal, and emulation methods to accelerate verification and improve debug.
• Drive verification across interfaces, bridges, protocol adaptation, ordering, flow-control, QoS, and error handling.
• Collaborate with architects and designers early to remove ambiguities and improve debugability.
• Perform failure analysis and root-cause debug across specification, RTL, test content, and verification infrastructure.
• Mentor engineers and influence reusable verification methodology and infrastructure.

Requirements

Must-have qualifications:

• 12+ years of CPU/core or SoC functional verification experience, including out-of-order core verification.
• Deep understanding of CPU microarchitecture and experience in Frontend, Midcore, Load-Store Unit, memory ordering/consistency, or hardware prefetch verification.
• Strong knowledge of cache-coherent systems, on-chip interconnects, ordering semantics, buffering, arbitration, and flow control.
• 8+ years direct experience in memory management verification (MMU/IOMMU).
• Proven verification methodology skills: test planning, stimulus generation, failure analysis, coverage analysis, and closure.
• Strong debug skills and ability to translate architectural intent into verification strategy and execution.
• Proficient software development, scripting, and automation skills for building scalable DV infrastructure.

Nice-to-have:

• Experience spanning high-performance CPU core verification and coherent interconnect or memory-subsystem verification in large SoCs.
• Subsystem integration experience, bridge-heavy designs, or complex protocol interactions.
• Experience applying formal verification to bounded/interface-heavy microarchitectural problems.
• Experience using emulation to accelerate verification on large workloads.
• Demonstrated technical leadership mentoring engineers and influencing cross-team methodology.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (specified in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.