Principal Design Verification Engineer – CPU Subsystem Power Management

Job Title

Principal Design Verification Engineer – CPU Subsystem Power Management

Role Summary

Principal technical lead responsible for verification strategy, execution, and signoff for CPU-subsystem power-management across core, cluster, LLC, and uncore domains. Focus on ensuring data-center-grade correctness, resiliency, and integration quality for features such as DVFS, retention, clock/reset sequencing, warm reset, and power gating.

The role partners with architecture, RTL, formal, performance, and DV teams to define verification scope, drive closure of critical corner cases, and deliver reusable methodology and infrastructure.

Experience Level

Senior / Principal level. Role expects 12+ years of relevant CPU/subsystem/SoC or ASIC functional verification experience.

Responsibilities

Lead verification planning and execution for CPU-subsystem power-management from unit blocks through subsystem integration and signoff.

• Define verification strategies, test plans, assertions, checkers, coverage models, and closure criteria for power-state transitions, clock/reset sequencing, retention, DVFS, warm reset, and multi-domain interactions.
• Drive verification across multiple bench contexts, including CoreIP, PMC unit-level, and broader PM unit and uncore environments.
• Own stress, corner-case, and long-run scenarios that expose failures in power-state sequencing, asynchronous clock relationships, retention recovery, and reset interactions.
• Perform efficient failure analysis and root-cause debug across specification, RTL, verification infra, assertions, and test stimulus.
• Apply appropriate verification methods: simulation, formal, power-aware verification, and emulation for subsystem-level signoff.
• Contribute reusable methodology, automation, and infrastructure to improve DV productivity and quality.
• Mentor engineers and provide technical leadership for difficult subsystem-level debug and closure challenges.
• Help define signoff expectations and closure discipline suitable for data-center-grade CPU subsystems.

Requirements

Key qualifications and skills required and preferred for success in this role.

Must-have

• 12+ years of relevant CPU, subsystem, SoC, or ASIC functional verification experience at a principal/technical-lead level.
• Direct, strong experience in CPU-subsystem power-management verification: clock/reset behavior, power-state transitions, retention, gating, and multi-domain interactions.
• Strong hands-on SystemVerilog-based verification experience, including scalable verification planning, assertions, checkers, coverage strategy, and debug workflows.
• Proven ability to translate architectural intent into effective verification strategy and execution plans.
• Software and scripting skills (Python or similar) for DV infrastructure and automation.
• Deep understanding of high-performance CPU subsystem behavior across core, cluster, cache, and uncore boundaries.
• Experience in root-cause analysis and cross-functional technical communication with architecture, RTL, DV, formal, and performance teams.
• 8+ years direct experience verifying memory management units / memory-management verification and familiarity with hypervisor/virtualization issues (memory/IO MMUs).
• Familiarity with object-oriented verification methodologies and good software engineering practices for DV environments.

Nice-to-have

• Experience with formal verification, power-aware simulation, and emulation for subsystem signoff.
• Experience developing checkers for live retention, cluster/tile retention, CCidle, and related PM correctness checks.
• Experience with PMC- or power-controller-centric verification flows and unit-level standalone benches.
• Track record of influencing verification methodology and delivering reusable DV infrastructure across teams.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (BS/MS/PhD in EE, CE, or CS). (Education stated in job qualifications.)

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.