Principal Design Verification Engineer – CPU Core LSU

Job Title

Principal Design Verification Engineer 6 CPU Core LSU

Role Summary

Lead verification strategy and execution for the CPU Core Load-Store Unit (LSU) in a high-performance out-of-order core. Work with architecture, RTL, formal, performance, and verification teams to identify microarchitectural risks and ensure signoff-quality verification.

Primary focus areas: load/store ordering, hazard handling, cache coherency, memory consistency, and building scalable verification infrastructure and methodologies.

Experience Level

Senior / Principal-level 6 typically requires 12+ years of relevant CPU/core or SoC functional verification experience and deep LSU and memory-subsystem expertise.

Responsibilities

Plan and execute verification activities for the CPU Core LSU at block and core levels; lead debugging, coverage closure, and mentorship.

• Lead verification strategy, planning, execution, debug, coverage analysis, and closure for the LSU at block and core level.
• Define and verify complex LSU behaviors: load/store ordering, dependency handling, hazard detection, barriers/fences, atomics, and weak-memory interactions.
• Verify cache-facing behaviors: cache hits/misses, snoops, evictions, coherency state interactions, and L1-to-downstream data correctness.
• Develop high-value checkers, scoreboards, assertions, stimulus strategies, and coverage models targeting coherency and consistency corner cases.
• Apply simulation, formal techniques, and emulation as appropriate to improve quality, accelerate turnaround, and aid debug on large verification workloads.
• Collaborate with architects and RTL designers early to review specifications, identify ambiguities, and improve debugability.
• Drive root-cause analysis across specification, RTL, test content, assertions, and verification infrastructure for difficult failures.
• Mentor engineers and influence methodology to create reusable verification approaches for future CPU cores and memory subsystems.

Requirements

Must-have:

• 12+ years of experience in CPU/core or SoC functional verification at a principal level.
• Direct experience with out-of-order core verification and strong CPU microarchitecture understanding.
• Deep expertise in Load-Store Unit verification, memory ordering, and memory-consistency issues.
• Strong understanding of cache-coherent systems and memory hierarchy verification (ordering, snooping, flow control).
• Proven skills in verification methodology: test planning, stimulus generation, failure analysis, coverage analysis, and closure.
• Strong debug skills and ability to translate architecture intent into effective verification strategy.
• Strong software development, scripting, and automation skills; experience with object-oriented programming principles.
• 8+ years direct experience on memory management (MMU) verification, including hypervisor/virtualization scenarios.

Nice-to-have:

• Experience with formal verification of LSU or memory-subsystem properties (load correctness, ordering, barriers, liveness).
• Experience with litmus-style or memory-model-oriented verification approaches and multicore memory-consistency verification.
• Experience verifying interactions between LSU, cache hierarchy, coherent interconnects, and memory subsystem boundaries in large SoCs.
• Experience collaborating with performance, compiler, software, formal, and system verification teams.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (explicitly listed in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.