Principal Design Verification Engineer — CPU Core Hardware Prefetch

Job Title

Principal Design Verification Engineer — CPU Core Hardware Prefetch

Role Summary

Lead verification strategy and execution for hardware prefetch in a high-performance out-of-order CPU core. Act as a technical lead across architecture, RTL, performance, software, and verification teams to identify microarchitectural risk, define tests, and achieve signoff quality.

Primary scope includes advanced prefetch behaviors, integration with the memory hierarchy, and improving verification methodology and reusable infrastructure across the CPU DV organization.

Experience Level

Senior-level. Requires 12+ years of relevant CPU/core or SoC functional verification experience consistent with a Principal-level role.

Responsibilities

Lead planning, execution, and signoff for hardware prefetch verification across unit and core contexts.

• Define verification strategy, test plans, checkers, scoreboards, assertions, and coverage models for prefetch microarchitecture.
• Verify stream allocation, training, replacement, prefetch generation, request replay/kill behavior, and issue-queue interactions.
• Validate runtime configurability through prefetch CSRs (enablement, windowing, distance limits, growth thresholds, queue controls).
• Verify interactions with DCache, MSHRs, L1/L2 targeting, and arbitration with other core traffic.
• Develop tests for corner cases: misconfirmation, untraining, queue unavailability, throttling, page-boundary behavior, and multi-stream scenarios.
• Use architectural counters, self-checking tests, and microarchitectural observability to validate correctness under performance-sensitive workloads.
• Apply simulation, formal techniques, emulation, and performance-oriented validation where appropriate.
• Drive efficient failure analysis, root-cause debug, and coordinate fixes across spec, RTL, tests, and infrastructure.
• Mentor engineers and shape reusable verification approaches and infrastructure for future CPU generations.

Requirements

Core technical and leadership requirements for successful candidates.

Must-have:

• 12+ years of CPU/core or SoC functional verification experience, including direct experience with out-of-order CPU core verification and strong CPU microarchitecture knowledge.
• Deep expertise in hardware prefetch or closely related memory-subsystem verification; able to translate architectural intent into an effective verification plan.
• Strong verification methodology skills: test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Proven debug skills and solid scripting/programming fundamentals for building scalable DV infrastructure and automation.
• Strong understanding of CPU memory behavior, ordering-sensitive interactions, cache hierarchy effects, and prefetch-demand interactions.
• Experience selecting and applying appropriate verification methods (simulation, formal, emulation) for high-risk or hard-to-observe behaviors.

Nice-to-have:

• Experience with stride/stream prefetchers, adaptive throttling, and advanced training/confirmation mechanisms.
• Experience using performance counters, constrained-random traffic, and software-driven stress patterns for validation.
• Experience with formal verification and emulation/acceleration for large CPU verification workloads.
• Demonstrated technical leadership, mentoring, and cross-team execution on complex CPU verification efforts.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (as specified in the posting).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.