Principal Design Verification Engineer – CPU Core Frontend

Job Title

Principal Design Verification Engineer – CPU Core Frontend

Role Summary

Lead verification strategy and execution for the CPU core frontend of a high-performance out-of-order processor. Primary focus on branch prediction, instruction fetch, frontend redirects and recovery, and interactions across the frontend pipeline.

Work closely with architecture, RTL, performance, and verification teams to identify microarchitectural risk early, improve verification quality, and deliver signoff-ready verification closure.

Experience Level

Senior — Principal level. Typical expectation: 12+ years of relevant CPU/core or SoC functional verification experience with significant leadership and technical ownership.

Responsibilities

Own verification planning and execution for frontend features and drive closure at block and core levels.

• Define verification strategy, test plans, checkers, assertions, stimulus, and coverage models for frontend microarchitecture.
• Lead verification of branch prediction and predictor state (direction, indirect/target prediction, return prediction, training/update, recovery).
• Lead verification of instruction fetch behavior (fetch packet correctness, PC sequencing, ordering, ITLB/translation interactions, cache-related fetch behavior, exception and redirect handling).
• Apply appropriate techniques (simulation, formal, emulation/acceleration) for high-risk or hard-to-observe behaviors.
• Partner with architects and RTL designers early to review specs, remove ambiguities, and improve debugability and testability.
• Perform coverage analysis, gap identification, bug triage, and drive signoff readiness for frontend features.
• Mentor engineers and shape reusable verification methodology and infrastructure across CPU DV teams.

Requirements

Must-have skills and experience for immediate impact; preferred items listed separately.

• 12+ years of CPU/core or SoC functional verification experience, including substantial experience with high-performance out-of-order CPUs.
• Direct, deep experience in CPU frontend verification: branch prediction, instruction fetch, redirects, and recovery.
• Strong understanding of CPU microarchitecture and ability to translate architectural intent into verification strategy.
• Proven experience with verification flow and methodology: test planning, stimulus generation, failure analysis, coverage analysis and closure.
• Strong debug skills for complex microarchitectural failures.
• Strong software and scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.
• Proven technical leadership and mentoring experience across verification teams.
• Authorization to work in the United States; employment contingent on background checks and any required export-control approvals.

Nice-to-have

• Experience with formal verification targeting control-heavy or interface-sensitive frontend problems.
• Experience using emulation or acceleration for large-scale CPU verification workloads.
• Experience with advanced frontend architectures (decoupled fetch/prediction) and BTB-style/target/return predictor microarchitectures.
• Experience collaborating with performance, compiler, system verification, and software teams to close verification gaps.
• Experience verifying memory management units, hypervisor/virtualization, or IO MMU verification.

Education Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field (specified in the posting as required).

About the Company

Company: SiFive

Headquarters: San Mateo, California, United States

SiFive is a pioneering company in the RISC-V ecosystem, focused on transforming the future of computing by delivering high-performance, data-intensive RISC-V solutions. Their compute platforms empower leading technology firms to innovate across various markets, including AI, machine learning, and automotive sectors. SiFive is recognized for its commitment to ongoing innovation and fostering collaboration among talented teams, impacting lives by enabling advanced chip design.