Principal Design Engineer (Virtual Solution)

Job Title

Principal Design Engineer (Virtual Solution)

Role Summary

Design and deliver system-level Accelerated Verification IP (AVIP) solutions for emulation and prototyping platforms to enable SoC and subsystem validation. Work with engineering teams and customers on solution architecture, integration, bring-up, and debugging.

Experience Level

Senior-level role. Typical experience: 5–10 years in verification, RTL, or system integration for complex SoC environments.

Responsibilities

Primary responsibilities include system architecture, integration, and customer enablement for emulation/prototyping verification solutions.

• Design and develop AVIP solutions for emulation/prototyping platforms (Palladium, Protium).
• Build and integrate accelerated VIP environments for complex SoC/subsystem validation.
• Develop end-to-end verification flows: AVIP integration, testbench and system modeling, bare-metal/driver validation.
• Architect scalable, multi-protocol, multi-clock-domain validation solutions optimized for emulation performance.
• Create custom test cases, tools, and automation for embedded, co‑emulation, and hybrid flows.
• Collaborate with product engineering, application engineers, and customers to debug and resolve system-level issues.
• Support customer enablement including bring-up, debug, and deployment of solutions.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 5–10 years of industry experience in verification, RTL, or system integration (experience guidance moved to Experience Level).
• Expertise in at least one high-speed protocol: PCIe, CXL, AMBA, UCIe, or Ethernet.
• Strong RTL design experience in SystemVerilog/Verilog.
• Proficient in C/C++ for modeling, testbench development, or system integration.
• Solid understanding of system-level verification methodologies and emulation/acceleration flows.
• Hands-on experience with Palladium, Protium, FPGA, or other emulation/prototyping platforms preferred.
• Strong debugging skills for complex system integration issues.
• Good English communication and ability to collaborate across global teams.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. (The posting specifies degree + 5–10 years' experience as the typical background.)

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.