Principal Design Engineer (SoC Chip Lead)
Lattice SemiconductorJob Title
Principal Design Engineer (SoC Chip Lead)
Role Summary
Lead architecture and delivery of complex SoC silicon and IP across configuration, security, processor, memory, and high-speed interfaces. Provide cross-functional technical leadership from system-level architecture and performance modeling through RTL, verification, and tape-out signoff.
Experience Level
Senior — Principal-level role. The posting specifies 20+ years of FPGA/SoC design experience.
Responsibilities
Primary responsibilities include system architecture, IP ownership, and delivery accountability for production silicon.
- Lead development of multi-chip modules (MCMs) and chiplet-based designs using 2.5D/3D advanced packaging across multiple program generations.
- Own chip tapeout and signoff with full accountability for chip quality and release to production.
- Provide cross-functional technical leadership across geographically distributed teams; translate product requirements into priorities and execution plans.
- Partner with architects, RTL teams, and software to evaluate architecture tradeoffs and drive hardware decisions across the SoC.
- Perform cycle-approximate performance modeling to enable architectural exploration and early software enablement.
- Quantify system-level tradeoffs across compute, memory bandwidth, and on-chip interconnect to inform reference architectures and strategy.
- Own system-level debug including floor-planning, power distribution, clocking, timing closure, and SI/PI activities.
- Define and execute IP roadmap with external IP vendors and conduct competitive benchmarking.
- Present technical status and roadmaps to executive leadership; identify new market and growth opportunities.
- Apply agentic AI methodologies to scale and accelerate design execution.
Requirements
Must-have technical skills, program experience, and leadership capabilities.
- 20+ years of FPGA/SoC design experience with a history of leading programs from concept to tape-out and production release.
- Expertise in SystemVerilog, synthesis flows, and static timing analysis.
- Deep practical knowledge across SoC domains: high-speed interfaces, system interconnects, and processor subsystems.
- Experience with 2.5D/3D packaging and chiplet-based architectures.
- Proven ability to develop system-level functional and performance models and ensure RTL correlation; support emulation-based pre-silicon validation.
- Define and own DFx methodologies (scan, BIST) and manufacturing test strategies from IP to chip level.
- Hands-on experience debugging complex designs via verification, emulation, and system validation.
- Demonstrated leadership in growing and directing geographically distributed, cross-functional engineering teams.
- Strong written and oral communication skills with experience presenting to executive audiences.
Education Requirements
BS, MS, or PhD in Electrical Engineering or Computer Engineering is specified. The posting pairs these degrees with the stated requirement of 20+ years of FPGA/SoC design experience. No certifications were specified.
About the Company
Company: Lattice Semiconductor
Headquarters: Portland, Oregon, USA
Lattice Semiconductor specializes in low power, small-form-factor programmable logic devices and solutions. The company is known for its innovative technology that enables a wide range of applications, including communication, consumer, and industrial markets.
